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llvm source #1

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define void @load_i32_stride6_vf4(<24 x i32>* %in.vec, <4 x i32>* %out.vec0, <4 x i32>* %out.vec1, <4 x i32>* %out.vec2, <4 x i32>* %out.vec3, <4 x i32>* %out.vec4, <4 x i32>* %out.vec5) nounwind {
  %wide.vec = load <24 x i32>, <24 x i32>* %in.vec, align 32

tail call void asm sideeffect "# LLVM-MCA-BEGIN", "~{dirflag},~{fpsr},~{flags}"()
  tail call void asm sideeffect "# LLVM-MCA-END", "~{dirflag},~{fpsr},~{flags}"()

%strided.vec0 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 0, i32 6, i32 12, i32 18>
  %strided.vec1 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 1, i32 7, i32 13, i32 19>
  %strided.vec2 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 2, i32 8, i32 14, i32 20>
  %strided.vec3 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 3, i32 9, i32 15, i32 21>
  %strided.vec4 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 4, i32 10, i32 16, i32 22>
  %strided.vec5 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 5, i32 11, i32 17, i32 23>

tail call void asm sideeffect "# LLVM-MCA-BEGIN", "~{dirflag},~{fpsr},~{flags}"()
  tail call void asm sideeffect "# LLVM-MCA-END", "~{dirflag},~{fpsr},~{flags}"()

store <4 x i32> %strided.vec0, <4 x i32>* %out.vec0, align 32
  store <4 x i32> %strided.vec1, <4 x i32>* %out.vec1, align 32
  store <4 x i32> %strided.vec2, <4 x i32>* %out.vec2, align 32
  store <4 x i32> %strided.vec3, <4 x i32>* %out.vec3, align 32
  store <4 x i32> %strided.vec4, <4 x i32>* %out.vec4, align 32
  store <4 x i32> %strided.vec5, <4 x i32>* %out.vec5, align 32

ret void
}

analysis source #2

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Source code

vpbroadcastd    xmm8, xmm8
        vmovdqa xmm4, xmmword ptr [rip + .LCPI0_0] # xmm4 = <0,6,4,u>
        vpblendd        ymm5, ymm1, ymm2, 48            # ymm5 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7]
        vpermd  ymm4, ymm4, ymm5
        vpshufd xmm6, xmm3, 170                 # xmm6 = xmm3[2,2,2,2]
        vpblendd        xmm10, xmm4, xmm6, 8            # xmm10 = xmm4[0,1,2],xmm6[3]
        vmovdqa xmm6, xmmword ptr [rip + .LCPI0_1] # xmm6 = <1,7,5,u>
        vpermd  ymm5, ymm6, ymm5
        vpblendd        xmm5, xmm5, xmm3, 8             # xmm5 = xmm5[0,1,2],xmm3[3]
        vpshufd xmm6, xmm7, 238                 # xmm6 = xmm7[2,3,2,3]
        vpshufd ymm9, ymm2, 224                 # ymm9 = ymm2[0,0,2,3,4,4,6,7]
        vpblendd        ymm6, ymm9, ymm6, 17            # ymm6 = ymm6[0],ymm9[1,2,3],ymm6[4],ymm9[5,6,7]
        vpermq  ymm6, ymm6, 236                 # ymm6 = ymm6[0,3,2,3]
        vpbroadcastd    xmm4, xmm0
        vpblendd        xmm4, xmm6, xmm4, 8             # xmm4 = xmm6[0,1,2],xmm4[3]
        vpshufd xmm6, xmm7, 255                 # xmm6 = xmm7[3,3,3,3]
        vpshufd ymm7, ymm2, 244                 # ymm7 = ymm2[0,1,3,3,4,5,7,7]
        vpblendd        ymm6, ymm7, ymm6, 17            # ymm6 = ymm6[0],ymm7[1,2,3],ymm6[4],ymm7[5,6,7]
        vpermq  ymm6, ymm6, 236                 # ymm6 = ymm6[0,3,2,3]
        vpblendd        xmm6, xmm6, xmm8, 8             # xmm6 = xmm6[0,1,2],xmm8[3]
        vpblendd        xmm7, xmm3, xmm0, 12            # xmm7 = xmm3[0,1],xmm0[2,3]
        vpshufd xmm7, xmm7, 132                 # xmm7 = xmm7[0,1,0,2]
        vmovdqa xmm8, xmmword ptr [rip + .LCPI0_2] # xmm8 = <4,2,u,u>
        vpblendd        ymm1, ymm2, ymm1, 48            # ymm1 = ymm2[0,1,2,3],ymm1[4,5],ymm2[6,7]
        vpermd  ymm2, ymm8, ymm1
        vpblendd        xmm2, xmm2, xmm7, 12            # xmm2 = xmm2[0,1],xmm7[2,3]
        vpmovzxdq       xmm3, xmm3              # xmm3 = xmm3[0],zero,xmm3[1],zero
        vpblendd        xmm0, xmm3, xmm0, 8             # xmm0 = xmm3[0,1,2],xmm0[3]
        vmovdqa xmm3, xmmword ptr [rip + .LCPI0_3] # xmm3 = <5,3,u,u>
        vpermd  ymm1, ymm3, ymm1
        vpblendd        xmm0, xmm1, xmm0, 12            # xmm0 = xmm1[0,1],xmm0[2,3]