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c++ source #1
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Compiler
6502-c++ 11.1.0
ARM GCC 10.2.0
ARM GCC 10.3.0
ARM GCC 10.4.0
ARM GCC 10.5.0
ARM GCC 11.1.0
ARM GCC 11.2.0
ARM GCC 11.3.0
ARM GCC 11.4.0
ARM GCC 12.1.0
ARM GCC 12.2.0
ARM GCC 12.3.0
ARM GCC 12.4.0
ARM GCC 12.5.0
ARM GCC 13.1.0
ARM GCC 13.2.0
ARM GCC 13.2.0 (unknown-eabi)
ARM GCC 13.3.0
ARM GCC 13.3.0 (unknown-eabi)
ARM GCC 13.4.0
ARM GCC 13.4.0 (unknown-eabi)
ARM GCC 14.1.0
ARM GCC 14.1.0 (unknown-eabi)
ARM GCC 14.2.0
ARM GCC 14.2.0 (unknown-eabi)
ARM GCC 14.3.0
ARM GCC 14.3.0 (unknown-eabi)
ARM GCC 15.1.0
ARM GCC 15.1.0 (unknown-eabi)
ARM GCC 15.2.0
ARM GCC 15.2.0 (unknown-eabi)
ARM GCC 4.5.4
ARM GCC 4.6.4
ARM GCC 5.4
ARM GCC 6.3.0
ARM GCC 6.4.0
ARM GCC 7.3.0
ARM GCC 7.5.0
ARM GCC 8.2.0
ARM GCC 8.5.0
ARM GCC 9.3.0
ARM GCC 9.4.0
ARM GCC 9.5.0
ARM GCC trunk
ARM gcc 10.2.1 (none)
ARM gcc 10.3.1 (2021.07 none)
ARM gcc 10.3.1 (2021.10 none)
ARM gcc 11.2.1 (none)
ARM gcc 5.4.1 (none)
ARM gcc 7.2.1 (none)
ARM gcc 8.2 (WinCE)
ARM gcc 8.3.1 (none)
ARM gcc 9.2.1 (none)
ARM msvc v19.0 (ex-WINE)
ARM msvc v19.10 (ex-WINE)
ARM msvc v19.14 (ex-WINE)
ARM64 Morello gcc 10.1 Alpha 2
ARM64 gcc 10.2
ARM64 gcc 10.3
ARM64 gcc 10.4
ARM64 gcc 10.5.0
ARM64 gcc 11.1
ARM64 gcc 11.2
ARM64 gcc 11.3
ARM64 gcc 11.4.0
ARM64 gcc 12.1
ARM64 gcc 12.2.0
ARM64 gcc 12.3.0
ARM64 gcc 12.4.0
ARM64 gcc 12.5.0
ARM64 gcc 13.1.0
ARM64 gcc 13.2.0
ARM64 gcc 13.3.0
ARM64 gcc 13.4.0
ARM64 gcc 14.1.0
ARM64 gcc 14.2.0
ARM64 gcc 14.3.0
ARM64 gcc 15.1.0
ARM64 gcc 15.2.0
ARM64 gcc 4.9.4
ARM64 gcc 5.4
ARM64 gcc 5.5.0
ARM64 gcc 6.3
ARM64 gcc 6.4
ARM64 gcc 7.3
ARM64 gcc 7.5
ARM64 gcc 8.2
ARM64 gcc 8.5
ARM64 gcc 9.3
ARM64 gcc 9.4
ARM64 gcc 9.5
ARM64 gcc trunk
ARM64 msvc v19.14 (ex-WINE)
AVR gcc 10.3.0
AVR gcc 11.1.0
AVR gcc 12.1.0
AVR gcc 12.2.0
AVR gcc 12.3.0
AVR gcc 12.4.0
AVR gcc 12.5.0
AVR gcc 13.1.0
AVR gcc 13.2.0
AVR gcc 13.3.0
AVR gcc 13.4.0
AVR gcc 14.1.0
AVR gcc 14.2.0
AVR gcc 14.3.0
AVR gcc 15.1.0
AVR gcc 15.2.0
AVR gcc 4.5.4
AVR gcc 4.6.4
AVR gcc 5.4.0
AVR gcc 9.2.0
AVR gcc 9.3.0
Arduino Mega (1.8.9)
Arduino Uno (1.8.9)
BPF clang (trunk)
BPF clang 13.0.0
BPF clang 14.0.0
BPF clang 15.0.0
BPF clang 16.0.0
BPF clang 17.0.1
BPF clang 18.1.0
BPF clang 19.1.0
BPF clang 20.1.0
BPF clang 21.1.0
EDG (experimental reflection)
EDG 6.5
EDG 6.5 (GNU mode gcc 13)
EDG 6.6
EDG 6.6 (GNU mode gcc 13)
EDG 6.7
EDG 6.7 (GNU mode gcc 14)
FRC 2019
FRC 2020
FRC 2023
HPPA gcc 14.2.0
HPPA gcc 14.3.0
HPPA gcc 15.1.0
HPPA gcc 15.2.0
KVX ACB 4.1.0 (GCC 7.5.0)
KVX ACB 4.1.0-cd1 (GCC 7.5.0)
KVX ACB 4.10.0 (GCC 10.3.1)
KVX ACB 4.11.1 (GCC 10.3.1)
KVX ACB 4.12.0 (GCC 11.3.0)
KVX ACB 4.2.0 (GCC 7.5.0)
KVX ACB 4.3.0 (GCC 7.5.0)
KVX ACB 4.4.0 (GCC 7.5.0)
KVX ACB 4.6.0 (GCC 9.4.1)
KVX ACB 4.8.0 (GCC 9.4.1)
KVX ACB 4.9.0 (GCC 9.4.1)
KVX ACB 5.0.0 (GCC 12.2.1)
KVX ACB 5.2.0 (GCC 13.2.1)
LoongArch64 clang (trunk)
LoongArch64 clang 17.0.1
LoongArch64 clang 18.1.0
LoongArch64 clang 19.1.0
LoongArch64 clang 20.1.0
LoongArch64 clang 21.1.0
M68K gcc 13.1.0
M68K gcc 13.2.0
M68K gcc 13.3.0
M68K gcc 13.4.0
M68K gcc 14.1.0
M68K gcc 14.2.0
M68K gcc 14.3.0
M68K gcc 15.1.0
M68K gcc 15.2.0
M68k clang (trunk)
MRISC32 gcc (trunk)
MSP430 gcc 4.5.3
MSP430 gcc 5.3.0
MSP430 gcc 6.2.1
MinGW clang 14.0.3
MinGW clang 14.0.6
MinGW clang 15.0.7
MinGW clang 16.0.0
MinGW clang 16.0.2
MinGW gcc 11.3.0
MinGW gcc 12.1.0
MinGW gcc 12.2.0
MinGW gcc 13.1.0
MinGW gcc 14.3.0
MinGW gcc 15.2.0
RISC-V (32-bits) gcc (trunk)
RISC-V (32-bits) gcc 10.2.0
RISC-V (32-bits) gcc 10.3.0
RISC-V (32-bits) gcc 11.2.0
RISC-V (32-bits) gcc 11.3.0
RISC-V (32-bits) gcc 11.4.0
RISC-V (32-bits) gcc 12.1.0
RISC-V (32-bits) gcc 12.2.0
RISC-V (32-bits) gcc 12.3.0
RISC-V (32-bits) gcc 12.4.0
RISC-V (32-bits) gcc 12.5.0
RISC-V (32-bits) gcc 13.1.0
RISC-V (32-bits) gcc 13.2.0
RISC-V (32-bits) gcc 13.3.0
RISC-V (32-bits) gcc 13.4.0
RISC-V (32-bits) gcc 14.1.0
RISC-V (32-bits) gcc 14.2.0
RISC-V (32-bits) gcc 14.3.0
RISC-V (32-bits) gcc 15.1.0
RISC-V (32-bits) gcc 15.2.0
RISC-V (32-bits) gcc 8.2.0
RISC-V (32-bits) gcc 8.5.0
RISC-V (32-bits) gcc 9.4.0
RISC-V (64-bits) gcc (trunk)
RISC-V (64-bits) gcc 10.2.0
RISC-V (64-bits) gcc 10.3.0
RISC-V (64-bits) gcc 11.2.0
RISC-V (64-bits) gcc 11.3.0
RISC-V (64-bits) gcc 11.4.0
RISC-V (64-bits) gcc 12.1.0
RISC-V (64-bits) gcc 12.2.0
RISC-V (64-bits) gcc 12.3.0
RISC-V (64-bits) gcc 12.4.0
RISC-V (64-bits) gcc 12.5.0
RISC-V (64-bits) gcc 13.1.0
RISC-V (64-bits) gcc 13.2.0
RISC-V (64-bits) gcc 13.3.0
RISC-V (64-bits) gcc 13.4.0
RISC-V (64-bits) gcc 14.1.0
RISC-V (64-bits) gcc 14.2.0
RISC-V (64-bits) gcc 14.3.0
RISC-V (64-bits) gcc 15.1.0
RISC-V (64-bits) gcc 15.2.0
RISC-V (64-bits) gcc 8.2.0
RISC-V (64-bits) gcc 8.5.0
RISC-V (64-bits) gcc 9.4.0
RISC-V rv32gc clang (trunk)
RISC-V rv32gc clang 10.0.0
RISC-V rv32gc clang 10.0.1
RISC-V rv32gc clang 11.0.0
RISC-V rv32gc clang 11.0.1
RISC-V rv32gc clang 12.0.0
RISC-V rv32gc clang 12.0.1
RISC-V rv32gc clang 13.0.0
RISC-V rv32gc clang 13.0.1
RISC-V rv32gc clang 14.0.0
RISC-V rv32gc clang 15.0.0
RISC-V rv32gc clang 16.0.0
RISC-V rv32gc clang 17.0.1
RISC-V rv32gc clang 18.1.0
RISC-V rv32gc clang 19.1.0
RISC-V rv32gc clang 20.1.0
RISC-V rv32gc clang 21.1.0
RISC-V rv32gc clang 9.0.0
RISC-V rv32gc clang 9.0.1
RISC-V rv64gc clang (trunk)
RISC-V rv64gc clang 10.0.0
RISC-V rv64gc clang 10.0.1
RISC-V rv64gc clang 11.0.0
RISC-V rv64gc clang 11.0.1
RISC-V rv64gc clang 12.0.0
RISC-V rv64gc clang 12.0.1
RISC-V rv64gc clang 13.0.0
RISC-V rv64gc clang 13.0.1
RISC-V rv64gc clang 14.0.0
RISC-V rv64gc clang 15.0.0
RISC-V rv64gc clang 16.0.0
RISC-V rv64gc clang 17.0.1
RISC-V rv64gc clang 18.1.0
RISC-V rv64gc clang 19.1.0
RISC-V rv64gc clang 20.1.0
RISC-V rv64gc clang 21.1.0
RISC-V rv64gc clang 9.0.0
RISC-V rv64gc clang 9.0.1
Raspbian Buster
Raspbian Stretch
SPARC LEON gcc 12.2.0
SPARC LEON gcc 12.3.0
SPARC LEON gcc 12.4.0
SPARC LEON gcc 12.5.0
SPARC LEON gcc 13.1.0
SPARC LEON gcc 13.2.0
SPARC LEON gcc 13.3.0
SPARC LEON gcc 13.4.0
SPARC LEON gcc 14.1.0
SPARC LEON gcc 14.2.0
SPARC LEON gcc 14.3.0
SPARC LEON gcc 15.1.0
SPARC LEON gcc 15.2.0
SPARC gcc 12.2.0
SPARC gcc 12.3.0
SPARC gcc 12.4.0
SPARC gcc 12.5.0
SPARC gcc 13.1.0
SPARC gcc 13.2.0
SPARC gcc 13.3.0
SPARC gcc 13.4.0
SPARC gcc 14.1.0
SPARC gcc 14.2.0
SPARC gcc 14.3.0
SPARC gcc 15.1.0
SPARC gcc 15.2.0
SPARC64 gcc 12.2.0
SPARC64 gcc 12.3.0
SPARC64 gcc 12.4.0
SPARC64 gcc 12.5.0
SPARC64 gcc 13.1.0
SPARC64 gcc 13.2.0
SPARC64 gcc 13.3.0
SPARC64 gcc 13.4.0
SPARC64 gcc 14.1.0
SPARC64 gcc 14.2.0
SPARC64 gcc 14.3.0
SPARC64 gcc 15.1.0
SPARC64 gcc 15.2.0
TI C6x gcc 12.2.0
TI C6x gcc 12.3.0
TI C6x gcc 12.4.0
TI C6x gcc 12.5.0
TI C6x gcc 13.1.0
TI C6x gcc 13.2.0
TI C6x gcc 13.3.0
TI C6x gcc 13.4.0
TI C6x gcc 14.1.0
TI C6x gcc 14.2.0
TI C6x gcc 14.3.0
TI C6x gcc 15.1.0
TI C6x gcc 15.2.0
TI CL430 21.6.1
Tricore gcc 11.3.0 (EEESlab)
VAX gcc NetBSDELF 10.4.0
VAX gcc NetBSDELF 10.5.0 (Nov 15 03:50:22 2023)
VAX gcc NetBSDELF 12.4.0 (Apr 16 05:27 2025)
WebAssembly clang (trunk)
Xtensa ESP32 gcc 11.2.0 (2022r1)
Xtensa ESP32 gcc 12.2.0 (20230208)
Xtensa ESP32 gcc 14.2.0 (20241119)
Xtensa ESP32 gcc 8.2.0 (2019r2)
Xtensa ESP32 gcc 8.2.0 (2020r1)
Xtensa ESP32 gcc 8.2.0 (2020r2)
Xtensa ESP32 gcc 8.4.0 (2020r3)
Xtensa ESP32 gcc 8.4.0 (2021r1)
Xtensa ESP32 gcc 8.4.0 (2021r2)
Xtensa ESP32-S2 gcc 11.2.0 (2022r1)
Xtensa ESP32-S2 gcc 12.2.0 (20230208)
Xtensa ESP32-S2 gcc 14.2.0 (20241119)
Xtensa ESP32-S2 gcc 8.2.0 (2019r2)
Xtensa ESP32-S2 gcc 8.2.0 (2020r1)
Xtensa ESP32-S2 gcc 8.2.0 (2020r2)
Xtensa ESP32-S2 gcc 8.4.0 (2020r3)
Xtensa ESP32-S2 gcc 8.4.0 (2021r1)
Xtensa ESP32-S2 gcc 8.4.0 (2021r2)
Xtensa ESP32-S3 gcc 11.2.0 (2022r1)
Xtensa ESP32-S3 gcc 12.2.0 (20230208)
Xtensa ESP32-S3 gcc 14.2.0 (20241119)
Xtensa ESP32-S3 gcc 8.4.0 (2020r3)
Xtensa ESP32-S3 gcc 8.4.0 (2021r1)
Xtensa ESP32-S3 gcc 8.4.0 (2021r2)
arm64 msvc v19.20 VS16.0
arm64 msvc v19.21 VS16.1
arm64 msvc v19.22 VS16.2
arm64 msvc v19.23 VS16.3
arm64 msvc v19.24 VS16.4
arm64 msvc v19.25 VS16.5
arm64 msvc v19.27 VS16.7
arm64 msvc v19.28 VS16.8
arm64 msvc v19.28 VS16.9
arm64 msvc v19.29 VS16.10
arm64 msvc v19.29 VS16.11
arm64 msvc v19.30 VS17.0
arm64 msvc v19.31 VS17.1
arm64 msvc v19.32 VS17.2
arm64 msvc v19.33 VS17.3
arm64 msvc v19.34 VS17.4
arm64 msvc v19.35 VS17.5
arm64 msvc v19.36 VS17.6
arm64 msvc v19.37 VS17.7
arm64 msvc v19.38 VS17.8
arm64 msvc v19.39 VS17.9
arm64 msvc v19.40 VS17.10
arm64 msvc v19.41 VS17.11
arm64 msvc v19.42 VS17.12
arm64 msvc v19.43 VS17.13
arm64 msvc v19.latest
armv7-a clang (trunk)
armv7-a clang 10.0.0
armv7-a clang 10.0.1
armv7-a clang 11.0.0
armv7-a clang 11.0.1
armv7-a clang 12.0.0
armv7-a clang 12.0.1
armv7-a clang 13.0.0
armv7-a clang 13.0.1
armv7-a clang 14.0.0
armv7-a clang 15.0.0
armv7-a clang 16.0.0
armv7-a clang 17.0.1
armv7-a clang 18.1.0
armv7-a clang 19.1.0
armv7-a clang 20.1.0
armv7-a clang 21.1.0
armv7-a clang 9.0.0
armv7-a clang 9.0.1
armv8-a clang (all architectural features, trunk)
armv8-a clang (trunk)
armv8-a clang 10.0.0
armv8-a clang 10.0.1
armv8-a clang 11.0.0
armv8-a clang 11.0.1
armv8-a clang 12.0.0
armv8-a clang 13.0.0
armv8-a clang 14.0.0
armv8-a clang 15.0.0
armv8-a clang 16.0.0
armv8-a clang 17.0.1
armv8-a clang 18.1.0
armv8-a clang 19.1.0
armv8-a clang 20.1.0
armv8-a clang 21.1.0
armv8-a clang 9.0.0
armv8-a clang 9.0.1
clad trunk (clang 21.1.0)
clad v1.10 (clang 20.1.0)
clad v1.8 (clang 18.1.0)
clad v1.9 (clang 19.1.0)
clad v2.00 (clang 20.1.0)
clang-cl 18.1.0
ellcc 0.1.33
ellcc 0.1.34
ellcc 2017-07-16
ez80-clang 15.0.0
ez80-clang 15.0.7
hexagon-clang 16.0.5
llvm-mos atari2600-3e
llvm-mos atari2600-4k
llvm-mos atari2600-common
llvm-mos atari5200-supercart
llvm-mos atari8-cart-megacart
llvm-mos atari8-cart-std
llvm-mos atari8-cart-xegs
llvm-mos atari8-common
llvm-mos atari8-dos
llvm-mos c128
llvm-mos c64
llvm-mos commodore
llvm-mos cpm65
llvm-mos cx16
llvm-mos dodo
llvm-mos eater
llvm-mos mega65
llvm-mos nes
llvm-mos nes-action53
llvm-mos nes-cnrom
llvm-mos nes-gtrom
llvm-mos nes-mmc1
llvm-mos nes-mmc3
llvm-mos nes-nrom
llvm-mos nes-unrom
llvm-mos nes-unrom-512
llvm-mos osi-c1p
llvm-mos pce
llvm-mos pce-cd
llvm-mos pce-common
llvm-mos pet
llvm-mos rp6502
llvm-mos rpc8e
llvm-mos supervision
llvm-mos vic20
loongarch64 gcc 12.2.0
loongarch64 gcc 12.3.0
loongarch64 gcc 12.4.0
loongarch64 gcc 12.5.0
loongarch64 gcc 13.1.0
loongarch64 gcc 13.2.0
loongarch64 gcc 13.3.0
loongarch64 gcc 13.4.0
loongarch64 gcc 14.1.0
loongarch64 gcc 14.2.0
loongarch64 gcc 14.3.0
loongarch64 gcc 15.1.0
loongarch64 gcc 15.2.0
mips clang 13.0.0
mips clang 14.0.0
mips clang 15.0.0
mips clang 16.0.0
mips clang 17.0.1
mips clang 18.1.0
mips clang 19.1.0
mips clang 20.1.0
mips clang 21.1.0
mips gcc 11.2.0
mips gcc 12.1.0
mips gcc 12.2.0
mips gcc 12.3.0
mips gcc 12.4.0
mips gcc 12.5.0
mips gcc 13.1.0
mips gcc 13.2.0
mips gcc 13.3.0
mips gcc 13.4.0
mips gcc 14.1.0
mips gcc 14.2.0
mips gcc 14.3.0
mips gcc 15.1.0
mips gcc 15.2.0
mips gcc 4.9.4
mips gcc 5.4
mips gcc 5.5.0
mips gcc 9.3.0 (codescape)
mips gcc 9.5.0
mips64 (el) gcc 12.1.0
mips64 (el) gcc 12.2.0
mips64 (el) gcc 12.3.0
mips64 (el) gcc 12.4.0
mips64 (el) gcc 12.5.0
mips64 (el) gcc 13.1.0
mips64 (el) gcc 13.2.0
mips64 (el) gcc 13.3.0
mips64 (el) gcc 13.4.0
mips64 (el) gcc 14.1.0
mips64 (el) gcc 14.2.0
mips64 (el) gcc 14.3.0
mips64 (el) gcc 15.1.0
mips64 (el) gcc 15.2.0
mips64 (el) gcc 4.9.4
mips64 (el) gcc 5.4.0
mips64 (el) gcc 5.5.0
mips64 (el) gcc 9.5.0
mips64 clang 13.0.0
mips64 clang 14.0.0
mips64 clang 15.0.0
mips64 clang 16.0.0
mips64 clang 17.0.1
mips64 clang 18.1.0
mips64 clang 19.1.0
mips64 clang 20.1.0
mips64 clang 21.1.0
mips64 gcc 11.2.0
mips64 gcc 12.1.0
mips64 gcc 12.2.0
mips64 gcc 12.3.0
mips64 gcc 12.4.0
mips64 gcc 12.5.0
mips64 gcc 13.1.0
mips64 gcc 13.2.0
mips64 gcc 13.3.0
mips64 gcc 13.4.0
mips64 gcc 14.1.0
mips64 gcc 14.2.0
mips64 gcc 14.3.0
mips64 gcc 15.1.0
mips64 gcc 15.2.0
mips64 gcc 4.9.4
mips64 gcc 5.4.0
mips64 gcc 5.5.0
mips64 gcc 9.5.0
mips64el clang 13.0.0
mips64el clang 14.0.0
mips64el clang 15.0.0
mips64el clang 16.0.0
mips64el clang 17.0.1
mips64el clang 18.1.0
mips64el clang 19.1.0
mips64el clang 20.1.0
mips64el clang 21.1.0
mipsel clang 13.0.0
mipsel clang 14.0.0
mipsel clang 15.0.0
mipsel clang 16.0.0
mipsel clang 17.0.1
mipsel clang 18.1.0
mipsel clang 19.1.0
mipsel clang 20.1.0
mipsel clang 21.1.0
mipsel gcc 12.1.0
mipsel gcc 12.2.0
mipsel gcc 12.3.0
mipsel gcc 12.4.0
mipsel gcc 12.5.0
mipsel gcc 13.1.0
mipsel gcc 13.2.0
mipsel gcc 13.3.0
mipsel gcc 13.4.0
mipsel gcc 14.1.0
mipsel gcc 14.2.0
mipsel gcc 14.3.0
mipsel gcc 15.1.0
mipsel gcc 15.2.0
mipsel gcc 4.9.4
mipsel gcc 5.4.0
mipsel gcc 5.5.0
mipsel gcc 9.5.0
nanoMIPS gcc 6.3.0 (mtk)
power gcc 11.2.0
power gcc 12.1.0
power gcc 12.2.0
power gcc 12.3.0
power gcc 12.4.0
power gcc 12.5.0
power gcc 13.1.0
power gcc 13.2.0
power gcc 13.3.0
power gcc 13.4.0
power gcc 14.1.0
power gcc 14.2.0
power gcc 14.3.0
power gcc 15.1.0
power gcc 15.2.0
power gcc 4.8.5
power64 AT12.0 (gcc8)
power64 AT13.0 (gcc9)
power64 gcc 11.2.0
power64 gcc 12.1.0
power64 gcc 12.2.0
power64 gcc 12.3.0
power64 gcc 12.4.0
power64 gcc 12.5.0
power64 gcc 13.1.0
power64 gcc 13.2.0
power64 gcc 13.3.0
power64 gcc 13.4.0
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z180-clang 15.0.0
z180-clang 15.0.7
z80-clang 15.0.0
z80-clang 15.0.7
zig c++ 0.10.0
zig c++ 0.11.0
zig c++ 0.12.0
zig c++ 0.12.1
zig c++ 0.13.0
zig c++ 0.14.0
zig c++ 0.14.1
zig c++ 0.15.1
zig c++ 0.6.0
zig c++ 0.7.0
zig c++ 0.7.1
zig c++ 0.8.0
zig c++ 0.9.0
zig c++ trunk
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Source code
#include <wasm_simd128.h> #include <stddef.h> #define QK_K 256 float abs_max_val_orig(float *x_block) { v128_t amax_vec = wasm_f32x4_splat(0.0f); v128_t max_vec = wasm_f32x4_splat(0.0f); // Vectorized max abs value search for (int j = 0; j < QK_K; j += 4) { v128_t x_vec = wasm_v128_load(x_block + j); v128_t abs_x = wasm_f32x4_abs(x_vec); v128_t mask = wasm_f32x4_gt(abs_x, amax_vec); amax_vec = wasm_v128_bitselect(abs_x, amax_vec, mask); max_vec = wasm_v128_bitselect(x_vec, max_vec, mask); } // Manual unroll for lane extraction float amax = wasm_f32x4_extract_lane(amax_vec, 0); float max_val = wasm_f32x4_extract_lane(max_vec, 0); #define UPDATE_MAX(lane) \ { \ float a = wasm_f32x4_extract_lane(amax_vec, lane); \ if (a > amax) { \ amax = a; \ max_val = wasm_f32x4_extract_lane(max_vec, lane); \ } \ } UPDATE_MAX(1) UPDATE_MAX(2) UPDATE_MAX(3) #undef UPDATE_MAX return max_val; } float abs_max_val_camel(float *x_block) { v128_t min_vec = wasm_v128_load(x_block); v128_t max_vec = min_vec; for (int j = 4; j < QK_K; j += 4) { v128_t x_vec = wasm_v128_load(x_block + j); max_vec = wasm_f32x4_pmax(max_vec, x_vec); min_vec = wasm_f32x4_pmin(min_vec, x_vec); } max_vec = wasm_f32x4_pmax(max_vec, wasm_i32x4_shuffle(max_vec, max_vec, 2, 3, 0, 1)); max_vec = wasm_f32x4_pmax(max_vec, wasm_i32x4_shuffle(max_vec, max_vec, 1, 0, 3, 2)); min_vec = wasm_f32x4_pmin(min_vec, wasm_i32x4_shuffle(min_vec, min_vec, 2, 3, 0, 1)); min_vec = wasm_f32x4_pmin(min_vec, wasm_i32x4_shuffle(min_vec, min_vec, 1, 0, 3, 2)); float max = wasm_f32x4_extract_lane(max_vec, 0); float min = wasm_f32x4_extract_lane(min_vec, 0); float max_val = -min > max ? min : max; return max_val; }
wasm source #2
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Wasmtime 20.0.1
Wasmtime 21.0.1
Wasmtime 22.0.0
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Source code
(module (type (;0;) (func (param i32) (result f32))) (import "env" "__linear_memory" (memory (;0;) 0)) (func $abs_max_val_orig (type 0) (param i32) (result f32) (local i32 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 f32 f32 f32) i32.const 0 local.set 1 v128.const i32x4 0x00000000 0x00000000 0x00000000 0x00000000 local.tee 2 local.set 3 block ;; label = @1 loop ;; label = @2 local.get 0 v128.load align=1 local.tee 4 local.get 3 local.get 4 f32x4.abs local.tee 4 local.get 2 f32x4.gt local.tee 5 v128.bitselect local.set 3 local.get 4 local.get 2 local.get 5 v128.bitselect local.set 2 local.get 1 i32.const 251 i32.gt_u br_if 1 (;@1;) local.get 0 i32.const 992 i32.add v128.load align=1 local.tee 4 local.get 0 i32.const 976 i32.add v128.load align=1 local.tee 5 local.get 0 i32.const 960 i32.add v128.load align=1 local.tee 6 local.get 0 i32.const 944 i32.add v128.load align=1 local.tee 7 local.get 0 i32.const 928 i32.add v128.load align=1 local.tee 8 local.get 0 i32.const 912 i32.add v128.load align=1 local.tee 9 local.get 0 i32.const 896 i32.add v128.load align=1 local.tee 10 local.get 0 i32.const 880 i32.add v128.load align=1 local.tee 11 local.get 0 i32.const 864 i32.add v128.load align=1 local.tee 12 local.get 0 i32.const 848 i32.add v128.load align=1 local.tee 13 local.get 0 i32.const 832 i32.add v128.load align=1 local.tee 14 local.get 0 i32.const 816 i32.add v128.load align=1 local.tee 15 local.get 0 i32.const 800 i32.add v128.load align=1 local.tee 16 local.get 0 i32.const 784 i32.add v128.load align=1 local.tee 17 local.get 0 i32.const 768 i32.add v128.load align=1 local.tee 18 local.get 0 i32.const 752 i32.add v128.load align=1 local.tee 19 local.get 0 i32.const 736 i32.add v128.load align=1 local.tee 20 local.get 0 i32.const 720 i32.add v128.load align=1 local.tee 21 local.get 0 i32.const 704 i32.add v128.load align=1 local.tee 22 local.get 0 i32.const 688 i32.add v128.load align=1 local.tee 23 local.get 0 i32.const 672 i32.add v128.load align=1 local.tee 24 local.get 0 i32.const 656 i32.add v128.load align=1 local.tee 25 local.get 0 i32.const 640 i32.add v128.load align=1 local.tee 26 local.get 0 i32.const 624 i32.add v128.load align=1 local.tee 27 local.get 0 i32.const 608 i32.add v128.load align=1 local.tee 28 local.get 0 i32.const 592 i32.add v128.load align=1 local.tee 29 local.get 0 i32.const 576 i32.add v128.load align=1 local.tee 30 local.get 0 i32.const 560 i32.add v128.load align=1 local.tee 31 local.get 0 i32.const 544 i32.add v128.load align=1 local.tee 32 local.get 0 i32.const 528 i32.add v128.load align=1 local.tee 33 local.get 0 i32.const 512 i32.add v128.load align=1 local.tee 34 local.get 0 i32.const 496 i32.add v128.load align=1 local.tee 35 local.get 0 i32.const 480 i32.add v128.load align=1 local.tee 36 local.get 0 i32.const 464 i32.add v128.load align=1 local.tee 37 local.get 0 i32.const 448 i32.add v128.load align=1 local.tee 38 local.get 0 i32.const 432 i32.add v128.load align=1 local.tee 39 local.get 0 i32.const 416 i32.add v128.load align=1 local.tee 40 local.get 0 i32.const 400 i32.add v128.load align=1 local.tee 41 local.get 0 i32.const 384 i32.add v128.load align=1 local.tee 42 local.get 0 i32.const 368 i32.add v128.load align=1 local.tee 43 local.get 0 i32.const 352 i32.add v128.load align=1 local.tee 44 local.get 0 i32.const 336 i32.add v128.load align=1 local.tee 45 local.get 0 i32.const 320 i32.add v128.load align=1 local.tee 46 local.get 0 i32.const 304 i32.add v128.load align=1 local.tee 47 local.get 0 i32.const 288 i32.add v128.load align=1 local.tee 48 local.get 0 i32.const 272 i32.add v128.load align=1 local.tee 49 local.get 0 i32.const 256 i32.add v128.load align=1 local.tee 50 local.get 0 i32.const 240 i32.add v128.load align=1 local.tee 51 local.get 0 i32.const 224 i32.add v128.load align=1 local.tee 52 local.get 0 i32.const 208 i32.add v128.load align=1 local.tee 53 local.get 0 i32.const 192 i32.add v128.load align=1 local.tee 54 local.get 0 i32.const 176 i32.add v128.load align=1 local.tee 55 local.get 0 i32.const 160 i32.add v128.load align=1 local.tee 56 local.get 0 i32.const 144 i32.add v128.load align=1 local.tee 57 local.get 0 i32.const 128 i32.add v128.load align=1 local.tee 58 local.get 0 i32.const 112 i32.add v128.load align=1 local.tee 59 local.get 0 i32.const 96 i32.add v128.load align=1 local.tee 60 local.get 0 i32.const 80 i32.add v128.load align=1 local.tee 61 local.get 0 i32.const 64 i32.add v128.load align=1 local.tee 62 local.get 0 i32.const 48 i32.add v128.load align=1 local.tee 63 local.get 0 i32.const 32 i32.add v128.load align=1 local.tee 64 local.get 0 i32.const 16 i32.add v128.load align=1 local.tee 65 local.get 3 local.get 65 f32x4.abs local.tee 65 local.get 2 f32x4.gt local.tee 66 v128.bitselect local.get 64 f32x4.abs local.tee 3 local.get 65 local.get 2 local.get 66 v128.bitselect local.tee 2 f32x4.gt local.tee 64 v128.bitselect local.get 63 f32x4.abs local.tee 63 local.get 3 local.get 2 local.get 64 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 62 f32x4.abs local.tee 62 local.get 63 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 61 f32x4.abs local.tee 61 local.get 62 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 60 f32x4.abs local.tee 60 local.get 61 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 59 f32x4.abs local.tee 59 local.get 60 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 58 f32x4.abs local.tee 58 local.get 59 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 57 f32x4.abs local.tee 57 local.get 58 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 56 f32x4.abs local.tee 56 local.get 57 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 55 f32x4.abs local.tee 55 local.get 56 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 54 f32x4.abs local.tee 54 local.get 55 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 53 f32x4.abs local.tee 53 local.get 54 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 52 f32x4.abs local.tee 52 local.get 53 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 51 f32x4.abs local.tee 51 local.get 52 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 50 f32x4.abs local.tee 50 local.get 51 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 49 f32x4.abs local.tee 49 local.get 50 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 48 f32x4.abs local.tee 48 local.get 49 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 47 f32x4.abs local.tee 47 local.get 48 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 46 f32x4.abs local.tee 46 local.get 47 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 45 f32x4.abs local.tee 45 local.get 46 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 44 f32x4.abs local.tee 44 local.get 45 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 43 f32x4.abs local.tee 43 local.get 44 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 42 f32x4.abs local.tee 42 local.get 43 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 41 f32x4.abs local.tee 41 local.get 42 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 40 f32x4.abs local.tee 40 local.get 41 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 39 f32x4.abs local.tee 39 local.get 40 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 38 f32x4.abs local.tee 38 local.get 39 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 37 f32x4.abs local.tee 37 local.get 38 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 36 f32x4.abs local.tee 36 local.get 37 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 35 f32x4.abs local.tee 35 local.get 36 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 34 f32x4.abs local.tee 34 local.get 35 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 33 f32x4.abs local.tee 33 local.get 34 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 32 f32x4.abs local.tee 32 local.get 33 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 31 f32x4.abs local.tee 31 local.get 32 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 30 f32x4.abs local.tee 30 local.get 31 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 29 f32x4.abs local.tee 29 local.get 30 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 28 f32x4.abs local.tee 28 local.get 29 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 27 f32x4.abs local.tee 27 local.get 28 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 26 f32x4.abs local.tee 26 local.get 27 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 25 f32x4.abs local.tee 25 local.get 26 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 24 f32x4.abs local.tee 24 local.get 25 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 23 f32x4.abs local.tee 23 local.get 24 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 22 f32x4.abs local.tee 22 local.get 23 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 21 f32x4.abs local.tee 21 local.get 22 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 20 f32x4.abs local.tee 20 local.get 21 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 19 f32x4.abs local.tee 19 local.get 20 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 18 f32x4.abs local.tee 18 local.get 19 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 17 f32x4.abs local.tee 17 local.get 18 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 16 f32x4.abs local.tee 16 local.get 17 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 15 f32x4.abs local.tee 15 local.get 16 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 14 f32x4.abs local.tee 14 local.get 15 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 13 f32x4.abs local.tee 13 local.get 14 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 12 f32x4.abs local.tee 12 local.get 13 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 11 f32x4.abs local.tee 11 local.get 12 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 10 f32x4.abs local.tee 10 local.get 11 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 9 f32x4.abs local.tee 9 local.get 10 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 8 f32x4.abs local.tee 8 local.get 9 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 7 f32x4.abs local.tee 7 local.get 8 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 6 f32x4.abs local.tee 6 local.get 7 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 5 f32x4.abs local.tee 5 local.get 6 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 3 v128.bitselect local.get 4 f32x4.abs local.tee 4 local.get 5 local.get 2 local.get 3 v128.bitselect local.tee 2 f32x4.gt local.tee 5 v128.bitselect local.set 3 local.get 4 local.get 2 local.get 5 v128.bitselect local.set 2 local.get 0 i32.const 1008 i32.add local.set 0 local.get 1 i32.const 252 i32.add local.set 1 br 0 (;@2;) end end local.get 3 f32x4.extract_lane 3 local.get 3 f32x4.extract_lane 2 local.get 3 f32x4.extract_lane 1 local.get 3 f32x4.extract_lane 0 local.get 2 f32x4.extract_lane 1 local.tee 67 local.get 2 f32x4.extract_lane 0 local.tee 68 f32.gt local.tee 0 select local.get 2 f32x4.extract_lane 2 local.tee 69 local.get 67 local.get 68 local.get 0 select local.tee 67 f32.gt local.tee 0 select local.get 2 f32x4.extract_lane 3 local.get 69 local.get 67 local.get 0 select f32.gt select) (func $abs_max_val_camel (type 0) (param i32) (result f32) (local v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 v128 f32 f32) local.get 0 v128.load align=1 local.tee 1 local.get 0 v128.load offset=16 align=1 local.tee 2 f32x4.pmin local.get 0 v128.load offset=32 align=1 local.tee 3 f32x4.pmin local.get 0 v128.load offset=48 align=1 local.tee 4 f32x4.pmin local.get 0 v128.load offset=64 align=1 local.tee 5 f32x4.pmin local.get 0 v128.load offset=80 align=1 local.tee 6 f32x4.pmin local.get 0 v128.load offset=96 align=1 local.tee 7 f32x4.pmin local.get 0 v128.load offset=112 align=1 local.tee 8 f32x4.pmin local.get 0 v128.load offset=128 align=1 local.tee 9 f32x4.pmin local.get 0 v128.load offset=144 align=1 local.tee 10 f32x4.pmin local.get 0 v128.load offset=160 align=1 local.tee 11 f32x4.pmin local.get 0 v128.load offset=176 align=1 local.tee 12 f32x4.pmin local.get 0 v128.load offset=192 align=1 local.tee 13 f32x4.pmin local.get 0 v128.load offset=208 align=1 local.tee 14 f32x4.pmin local.get 0 v128.load offset=224 align=1 local.tee 15 f32x4.pmin local.get 0 v128.load offset=240 align=1 local.tee 16 f32x4.pmin local.get 0 v128.load offset=256 align=1 local.tee 17 f32x4.pmin local.get 0 v128.load offset=272 align=1 local.tee 18 f32x4.pmin local.get 0 v128.load offset=288 align=1 local.tee 19 f32x4.pmin local.get 0 v128.load offset=304 align=1 local.tee 20 f32x4.pmin local.get 0 v128.load offset=320 align=1 local.tee 21 f32x4.pmin local.get 0 v128.load offset=336 align=1 local.tee 22 f32x4.pmin local.get 0 v128.load offset=352 align=1 local.tee 23 f32x4.pmin local.get 0 v128.load offset=368 align=1 local.tee 24 f32x4.pmin local.get 0 v128.load offset=384 align=1 local.tee 25 f32x4.pmin local.get 0 v128.load offset=400 align=1 local.tee 26 f32x4.pmin local.get 0 v128.load offset=416 align=1 local.tee 27 f32x4.pmin local.get 0 v128.load offset=432 align=1 local.tee 28 f32x4.pmin local.get 0 v128.load offset=448 align=1 local.tee 29 f32x4.pmin local.get 0 v128.load offset=464 align=1 local.tee 30 f32x4.pmin local.get 0 v128.load offset=480 align=1 local.tee 31 f32x4.pmin local.get 0 v128.load offset=496 align=1 local.tee 32 f32x4.pmin local.get 0 v128.load offset=512 align=1 local.tee 33 f32x4.pmin local.get 0 v128.load offset=528 align=1 local.tee 34 f32x4.pmin local.get 0 v128.load offset=544 align=1 local.tee 35 f32x4.pmin local.get 0 v128.load offset=560 align=1 local.tee 36 f32x4.pmin local.get 0 v128.load offset=576 align=1 local.tee 37 f32x4.pmin local.get 0 v128.load offset=592 align=1 local.tee 38 f32x4.pmin local.get 0 v128.load offset=608 align=1 local.tee 39 f32x4.pmin local.get 0 v128.load offset=624 align=1 local.tee 40 f32x4.pmin local.get 0 v128.load offset=640 align=1 local.tee 41 f32x4.pmin local.get 0 v128.load offset=656 align=1 local.tee 42 f32x4.pmin local.get 0 v128.load offset=672 align=1 local.tee 43 f32x4.pmin local.get 0 v128.load offset=688 align=1 local.tee 44 f32x4.pmin local.get 0 v128.load offset=704 align=1 local.tee 45 f32x4.pmin local.get 0 v128.load offset=720 align=1 local.tee 46 f32x4.pmin local.get 0 v128.load offset=736 align=1 local.tee 47 f32x4.pmin local.get 0 v128.load offset=752 align=1 local.tee 48 f32x4.pmin local.get 0 v128.load offset=768 align=1 local.tee 49 f32x4.pmin local.get 0 v128.load offset=784 align=1 local.tee 50 f32x4.pmin local.get 0 v128.load offset=800 align=1 local.tee 51 f32x4.pmin local.get 0 v128.load offset=816 align=1 local.tee 52 f32x4.pmin local.get 0 v128.load offset=832 align=1 local.tee 53 f32x4.pmin local.get 0 v128.load offset=848 align=1 local.tee 54 f32x4.pmin local.get 0 v128.load offset=864 align=1 local.tee 55 f32x4.pmin local.get 0 v128.load offset=880 align=1 local.tee 56 f32x4.pmin local.get 0 v128.load offset=896 align=1 local.tee 57 f32x4.pmin local.get 0 v128.load offset=912 align=1 local.tee 58 f32x4.pmin local.get 0 v128.load offset=928 align=1 local.tee 59 f32x4.pmin local.get 0 v128.load offset=944 align=1 local.tee 60 f32x4.pmin local.get 0 v128.load offset=960 align=1 local.tee 61 f32x4.pmin local.get 0 v128.load offset=976 align=1 local.tee 62 f32x4.pmin local.get 0 v128.load offset=992 align=1 local.tee 63 f32x4.pmin local.get 0 v128.load offset=1008 align=1 local.tee 64 f32x4.pmin local.tee 65 local.get 65 local.get 65 i8x16.shuffle 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 f32x4.pmin local.tee 65 local.get 65 local.get 65 i8x16.shuffle 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 f32x4.pmin f32x4.extract_lane 0 local.tee 66 local.get 1 local.get 2 f32x4.pmax local.get 3 f32x4.pmax local.get 4 f32x4.pmax local.get 5 f32x4.pmax local.get 6 f32x4.pmax local.get 7 f32x4.pmax local.get 8 f32x4.pmax local.get 9 f32x4.pmax local.get 10 f32x4.pmax local.get 11 f32x4.pmax local.get 12 f32x4.pmax local.get 13 f32x4.pmax local.get 14 f32x4.pmax local.get 15 f32x4.pmax local.get 16 f32x4.pmax local.get 17 f32x4.pmax local.get 18 f32x4.pmax local.get 19 f32x4.pmax local.get 20 f32x4.pmax local.get 21 f32x4.pmax local.get 22 f32x4.pmax local.get 23 f32x4.pmax local.get 24 f32x4.pmax local.get 25 f32x4.pmax local.get 26 f32x4.pmax local.get 27 f32x4.pmax local.get 28 f32x4.pmax local.get 29 f32x4.pmax local.get 30 f32x4.pmax local.get 31 f32x4.pmax local.get 32 f32x4.pmax local.get 33 f32x4.pmax local.get 34 f32x4.pmax local.get 35 f32x4.pmax local.get 36 f32x4.pmax local.get 37 f32x4.pmax local.get 38 f32x4.pmax local.get 39 f32x4.pmax local.get 40 f32x4.pmax local.get 41 f32x4.pmax local.get 42 f32x4.pmax local.get 43 f32x4.pmax local.get 44 f32x4.pmax local.get 45 f32x4.pmax local.get 46 f32x4.pmax local.get 47 f32x4.pmax local.get 48 f32x4.pmax local.get 49 f32x4.pmax local.get 50 f32x4.pmax local.get 51 f32x4.pmax local.get 52 f32x4.pmax local.get 53 f32x4.pmax local.get 54 f32x4.pmax local.get 55 f32x4.pmax local.get 56 f32x4.pmax local.get 57 f32x4.pmax local.get 58 f32x4.pmax local.get 59 f32x4.pmax local.get 60 f32x4.pmax local.get 61 f32x4.pmax local.get 62 f32x4.pmax local.get 63 f32x4.pmax local.get 64 f32x4.pmax local.tee 65 local.get 65 local.get 65 i8x16.shuffle 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 f32x4.pmax local.tee 65 local.get 65 local.get 65 i8x16.shuffle 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 f32x4.pmax f32x4.extract_lane 0 local.tee 67 local.get 67 local.get 66 f32.neg f32.lt select))
analysis source #4
Output
Compile to binary object
Link to binary
Execute the code
Intel asm syntax
Demangle identifiers
Verbose demangling
Filters
Unused labels
Library functions
Directives
Comments
Horizontal whitespace
Debug intrinsics
Compiler
OSACA (0.7.1)
llvm-mca (assertions trunk)
llvm-mca (trunk)
Options
Source code
abs_max_val_orig: push rbp mov rbp, rsp mov r10, qword ptr [rdi + 0x8] mov r10, qword ptr [r10] add r10, 0x930 cmp r10, rsp ja lbl1 sub rsp, 0x930 vpxor xmm14, xmm5, xmm5 movdqu xmmword ptr [rsp], xmm14 xor r11d, r11d mov r8, qword ptr [rdi + 0x58] mov r8, qword ptr [r8] movdqu xmm0, xmmword ptr [rsp] movdqu xmmword ptr [rsp + 0x10], xmm0 mov r9d, edx vmovdqu xmm3, xmmword ptr [r8 + r9] movdqu xmmword ptr [rsp + 0x920], xmm3 cmp r11d, 0xfb ja lbl2 lea r10d, [rdx + 0x3e0] vmovdqu xmm2, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x910], xmm2 lea r10d, [rdx + 0x3d0] vmovdqu xmm3, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x900], xmm3 lea r10d, [rdx + 0x3c0] vmovdqu xmm4, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8f0], xmm4 lea r10d, [rdx + 0x3b0] vmovdqu xmm5, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8e0], xmm5 lea r10d, [rdx + 0x3a0] vmovdqu xmm6, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8d0], xmm6 lea r10d, [rdx + 0x390] vmovdqu xmm7, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8c0], xmm7 lea r10d, [rdx + 0x380] vmovdqu xmm0, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8b0], xmm0 lea r10d, [rdx + 0x370] vmovdqu xmm9, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x8a0], xmm9 lea r10d, [rdx + 0x360] vmovdqu xmm10, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x890], xmm10 lea r10d, [rdx + 0x350] vmovdqu xmm11, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x880], xmm11 lea r10d, [rdx + 0x340] vmovdqu xmm12, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x870], xmm12 lea r10d, [rdx + 0x330] vmovdqu xmm14, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x860], xmm14 lea r10d, [rdx + 0x320] vmovdqu xmm2, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x850], xmm2 lea r10d, [rdx + 0x310] vmovdqu xmm8, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x840], xmm8 lea r10d, [rdx + 0x300] vmovdqu xmm4, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x830], xmm4 lea r10d, [rdx + 0x2f0] vmovdqu xmm3, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x820], xmm3 lea r10d, [rdx + 0x2e0] vmovdqu xmm15, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x810], xmm15 lea r10d, [rdx + 0x2d0] vmovdqu xmm5, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x800], xmm5 lea r10d, [rdx + 0x2c0] vmovdqu xmm6, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7f0], xmm6 lea r10d, [rdx + 0x2b0] vmovdqu xmm7, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7e0], xmm7 lea r10d, [rdx + 0x2a0] vmovdqu xmm0, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7d0], xmm0 lea r10d, [rdx + 0x290] vmovdqu xmm9, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7c0], xmm9 lea r10d, [rdx + 0x280] vmovdqu xmm10, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7b0], xmm10 lea r10d, [rdx + 0x270] vmovdqu xmm11, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x7a0], xmm11 lea r10d, [rdx + 0x260] vmovdqu xmm12, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x790], xmm12 lea r10d, [rdx + 0x250] vmovdqu xmm2, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x780], xmm2 lea r10d, [rdx + 0x240] vmovdqu xmm4, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x770], xmm4 lea r10d, [rdx + 0x230] vmovdqu xmm3, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x760], xmm3 lea r10d, [rdx + 0x220] vmovdqu xmm13, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x750], xmm13 lea r10d, [rdx + 0x210] vmovdqu xmm8, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x740], xmm8 lea r10d, [rdx + 0x200] vmovdqu xmm6, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x730], xmm6 lea r10d, [rdx + 0x1f0] vmovdqu xmm5, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x720], xmm5 lea r10d, [rdx + 0x1e0] vmovdqu xmm15, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x710], xmm15 lea r10d, [rdx + 0x1d0] vmovdqu xmm7, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x700], xmm7 lea r10d, [rdx + 0x1c0] vmovdqu xmm0, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6f0], xmm0 lea r10d, [rdx + 0x1b0] vmovdqu xmm9, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6e0], xmm9 lea r10d, [rdx + 0x1a0] vmovdqu xmm10, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6d0], xmm10 lea r10d, [rdx + 0x190] vmovdqu xmm11, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6c0], xmm11 lea r10d, [rdx + 0x180] vmovdqu xmm12, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6b0], xmm12 lea r10d, [rdx + 0x170] vmovdqu xmm2, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x6a0], xmm2 lea r10d, [rdx + 0x160] vmovdqu xmm3, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x690], xmm3 lea r10d, [rdx + 0x150] vmovdqu xmm13, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x680], xmm13 lea r10d, [rdx + 0x140] vmovdqu xmm14, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x670], xmm14 lea r10d, [rdx + 0x130] vmovdqu xmm5, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x660], xmm5 lea r10d, [rdx + 0x120] vmovdqu xmm15, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x650], xmm15 lea r10d, [rdx + 0x110] vmovdqu xmm6, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x640], xmm6 lea r10d, [rdx + 0x100] vmovdqu xmm0, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x630], xmm0 lea r10d, [rdx + 0xf0] vmovdqu xmm7, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x620], xmm7 lea r10d, [rdx + 0xe0] vmovdqu xmm8, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x610], xmm8 lea r10d, [rdx + 0xd0] vmovdqu xmm9, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x600], xmm9 lea r10d, [rdx + 0xc0] vmovdqu xmm10, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5f0], xmm10 lea r10d, [rdx + 0xb0] vmovdqu xmm2, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5e0], xmm2 lea r10d, [rdx + 0xa0] vmovdqu xmm1, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5d0], xmm1 lea r10d, [rdx + 0x90] vmovdqu xmm11, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5c0], xmm11 lea r10d, [rdx + 0x80] vmovdqu xmm11, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5b0], xmm11 lea r10d, [rdx + 0x70] vmovdqu xmm13, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x5a0], xmm13 lea r10d, [rdx + 0x60] vmovdqu xmm5, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x590], xmm5 lea r10d, [rdx + 0x50] vmovdqu xmm15, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x580], xmm15 lea r10d, [rdx + 0x40] vmovdqu xmm14, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x570], xmm14 lea r10d, [rdx + 0x30] vmovdqu xmm6, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x560], xmm6 lea r10d, [rdx + 0x20] vmovdqu xmm7, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x550], xmm7 lea r10d, [rdx + 0x10] vmovdqu xmm8, xmmword ptr [r8 + r10] movdqu xmmword ptr [rsp + 0x540], xmm8 add edx, 0x3f0 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm4, xmmword ptr [rsp + 0x910] vandps xmm5, xmm4, xmm2 movdqu xmmword ptr [rsp + 0x530], xmm5 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x900] vandps xmm0, xmm5, xmm2 movdqu xmmword ptr [rsp + 0x520], xmm0 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm8, xmmword ptr [rsp + 0x8f0] vandps xmm9, xmm8, xmm2 movdqu xmmword ptr [rsp + 0x510], xmm9 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x8e0] vandps xmm10, xmm7, xmm2 movdqu xmmword ptr [rsp + 0x500], xmm10 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm0, xmmword ptr [rsp + 0x8d0] vandps xmm2, xmm0, xmm2 movdqu xmmword ptr [rsp + 0x4f0], xmm2 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm10, xmmword ptr [rsp + 0x8c0] vandps xmm12, xmm10, xmm2 movdqu xmmword ptr [rsp + 0x4e0], xmm12 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm12, xmmword ptr [rsp + 0x8b0] vandps xmm11, xmm12, xmm2 movdqu xmmword ptr [rsp + 0x4d0], xmm11 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm3, xmmword ptr [rsp + 0x8a0] vandps xmm1, xmm3, xmm2 movdqu xmmword ptr [rsp + 0x4c0], xmm1 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm13, xmmword ptr [rsp + 0x890] vandps xmm3, xmm13, xmm2 movdqu xmmword ptr [rsp + 0x4b0], xmm3 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm4, xmmword ptr [rsp + 0x880] vandps xmm13, xmm4, xmm2 movdqu xmmword ptr [rsp + 0x4a0], xmm13 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm15, xmmword ptr [rsp + 0x870] vandps xmm5, xmm15, xmm2 movdqu xmmword ptr [rsp + 0x490], xmm5 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x860] vandps xmm4, xmm7, xmm2 movdqu xmmword ptr [rsp + 0x480], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm8, xmmword ptr [rsp + 0x850] vandps xmm15, xmm8, xmm2 movdqu xmmword ptr [rsp + 0x470], xmm15 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm8, xmmword ptr [rsp + 0x840] vandps xmm6, xmm8, xmm2 movdqu xmmword ptr [rsp + 0x460], xmm6 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm0, xmmword ptr [rsp + 0x830] vandps xmm7, xmm0, xmm2 movdqu xmmword ptr [rsp + 0x450], xmm7 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm9, xmmword ptr [rsp + 0x820] vandps xmm8, xmm9, xmm2 movdqu xmmword ptr [rsp + 0x440], xmm8 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm9, xmmword ptr [rsp + 0x810] vandps xmm0, xmm9, xmm2 movdqu xmmword ptr [rsp + 0x430], xmm0 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm10, xmmword ptr [rsp + 0x800] vandps xmm9, xmm10, xmm2 movdqu xmmword ptr [rsp + 0x420], xmm9 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm3, xmm0, 0x1 movdqu xmm2, xmmword ptr [rsp + 0x7f0] vandps xmm10, xmm2, xmm3 movdqu xmmword ptr [rsp + 0x410], xmm10 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm11, xmmword ptr [rsp + 0x7e0] vandps xmm2, xmm11, xmm2 movdqu xmmword ptr [rsp + 0x400], xmm2 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm11, xmmword ptr [rsp + 0x7d0] vandps xmm12, xmm11, xmm2 movdqu xmmword ptr [rsp + 0x3f0], xmm12 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x7c0] vandps xmm11, xmm1, xmm2 movdqu xmmword ptr [rsp + 0x3e0], xmm11 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x7b0] vandps xmm4, xmm1, xmm2 movdqu xmmword ptr [rsp + 0x3d0], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm3, xmmword ptr [rsp + 0x7a0] vandps xmm1, xmm3, xmm2 movdqu xmmword ptr [rsp + 0x3c0], xmm1 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm13, xmmword ptr [rsp + 0x790] vandps xmm4, xmm13, xmm2 movdqu xmmword ptr [rsp + 0x3b0], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x780] vandps xmm4, xmm5, xmm2 movdqu xmmword ptr [rsp + 0x3a0], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm14, xmmword ptr [rsp + 0x770] vandps xmm4, xmm14, xmm2 movdqu xmmword ptr [rsp + 0x390], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm15, xmmword ptr [rsp + 0x760] vandps xmm14, xmm15, xmm2 movdqu xmmword ptr [rsp + 0x380], xmm14 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm15, xmmword ptr [rsp + 0x750] vandps xmm4, xmm15, xmm2 movdqu xmmword ptr [rsp + 0x370], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x740] vandps xmm6, xmm7, xmm2 movdqu xmmword ptr [rsp + 0x360], xmm6 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x730] vandps xmm4, xmm7, xmm2 movdqu xmmword ptr [rsp + 0x350], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm8, xmmword ptr [rsp + 0x720] vandps xmm4, xmm8, xmm2 movdqu xmmword ptr [rsp + 0x130], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm0, xmmword ptr [rsp + 0x710] vandps xmm4, xmm0, xmm2 movdqu xmmword ptr [rsp + 0x120], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm9, xmmword ptr [rsp + 0x700] vandps xmm4, xmm9, xmm2 movdqu xmmword ptr [rsp + 0x110], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm9, xmmword ptr [rsp + 0x6f0] vandps xmm10, xmm9, xmm2 movdqu xmmword ptr [rsp + 0x100], xmm10 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm10, xmmword ptr [rsp + 0x6e0] vandps xmm2, xmm10, xmm2 movdqu xmmword ptr [rsp + 0xf0], xmm2 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm3, xmm0, 0x1 movdqu xmm2, xmmword ptr [rsp + 0x6d0] vandps xmm1, xmm2, xmm3 movdqu xmmword ptr [rsp + 0xe0], xmm1 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm12, xmmword ptr [rsp + 0x6c0] vandps xmm11, xmm12, xmm2 movdqu xmmword ptr [rsp + 0xd0], xmm11 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm11, xmmword ptr [rsp + 0x6b0] vandps xmm3, xmm11, xmm2 movdqu xmmword ptr [rsp + 0xc0], xmm3 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x6a0] vandps xmm13, xmm1, xmm2 movdqu xmmword ptr [rsp + 0xb0], xmm13 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x690] vandps xmm5, xmm1, xmm2 movdqu xmmword ptr [rsp + 0xa0], xmm5 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm3, xmmword ptr [rsp + 0x680] vandps xmm4, xmm3, xmm2 movdqu xmmword ptr [rsp + 0x90], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm13, xmmword ptr [rsp + 0x670] vandps xmm7, xmm13, xmm2 movdqu xmmword ptr [rsp + 0x80], xmm7 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x660] vandps xmm14, xmm5, xmm2 movdqu xmmword ptr [rsp + 0x70], xmm14 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm4, xmmword ptr [rsp + 0x650] vandps xmm8, xmm4, xmm2 movdqu xmmword ptr [rsp + 0x60], xmm8 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm14, xmmword ptr [rsp + 0x640] vandps xmm7, xmm14, xmm2 movdqu xmmword ptr [rsp + 0x50], xmm7 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm14, xmmword ptr [rsp + 0x630] vandps xmm4, xmm14, xmm2 movdqu xmmword ptr [rsp + 0x40], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm15, xmmword ptr [rsp + 0x620] vandps xmm5, xmm15, xmm2 movdqu xmmword ptr [rsp + 0x30], xmm5 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm6, xmmword ptr [rsp + 0x610] vandps xmm4, xmm6, xmm2 movdqu xmmword ptr [rsp + 0x20], xmm4 vpcmpeqd xmm0, xmm6, xmm6 vpsrld xmm2, xmm0, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x600] vandps xmm6, xmm7, xmm2 vpcmpeqd xmm0, xmm7, xmm7 vpsrld xmm2, xmm0, 0x1 movdqu xmm8, xmmword ptr [rsp + 0x5f0] vandps xmm0, xmm8, xmm2 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm2, xmm1, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x5e0] vandps xmm2, xmm1, xmm2 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm3, xmm1, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x5d0] vandps xmm3, xmm7, xmm3 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm9, xmmword ptr [rsp + 0x5c0] vandps xmm12, xmm9, xmm4 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm10, xmmword ptr [rsp + 0x5b0] vandps xmm13, xmm10, xmm4 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x5a0] vandps xmm15, xmm1, xmm4 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm1, xmmword ptr [rsp + 0x590] vandps xmm9, xmm1, xmm4 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm11, xmmword ptr [rsp + 0x580] vandps xmm10, xmm11, xmm4 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm5, xmm1, 0x1 movdqu xmm4, xmmword ptr [rsp + 0x570] vandps xmm11, xmm4, xmm5 vpcmpeqd xmm1, xmm7, xmm7 vpsrld xmm4, xmm1, 0x1 movdqu xmm7, xmmword ptr [rsp + 0x560] vandps xmm1, xmm7, xmm4 vpcmpeqd xmm4, xmm7, xmm7 vpsrld xmm4, xmm4, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x550] vandps xmm14, xmm5, xmm4 vpcmpeqd xmm4, xmm7, xmm7 vpsrld xmm4, xmm4, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x540] vandps xmm7, xmm5, xmm4 vpcmpeqd xmm4, xmm4, xmm4 vpsrld xmm4, xmm4, 0x1 movdqu xmm5, xmmword ptr [rsp + 0x920] vandps xmm4, xmm5, xmm4 movdqu xmm8, xmmword ptr [rsp + 0x10] vcmpltps xmm5, xmm8, xmm4 vpblendvb xmm4, xmm8, xmm4, xmm5 movdqu xmmword ptr [rsp + 0x340], xmm5 vcmpltps xmm5, xmm4, xmm7 vpblendvb xmm4, xmm4, xmm7, xmm5 movdqu xmmword ptr [rsp + 0x330], xmm5 vcmpltps xmm5, xmm4, xmm14 vpblendvb xmm4, xmm4, xmm14, xmm5 movdqu xmmword ptr [rsp + 0x320], xmm5 vcmpltps xmm8, xmm4, xmm1 vpblendvb xmm1, xmm4, xmm1, xmm8 movdqu xmmword ptr [rsp + 0x310], xmm8 vcmpltps xmm4, xmm1, xmm11 vpblendvb xmm1, xmm1, xmm11, xmm4 movdqu xmmword ptr [rsp + 0x300], xmm4 vcmpltps xmm4, xmm1, xmm10 vpblendvb xmm1, xmm1, xmm10, xmm4 movdqu xmmword ptr [rsp + 0x2f0], xmm4 vcmpltps xmm10, xmm1, xmm9 vpblendvb xmm1, xmm1, xmm9, xmm10 movdqu xmmword ptr [rsp + 0x2e0], xmm10 vcmpltps xmm4, xmm1, xmm15 vpblendvb xmm1, xmm1, xmm15, xmm4 movdqu xmmword ptr [rsp + 0x2d0], xmm4 vcmpltps xmm4, xmm1, xmm13 vpblendvb xmm1, xmm1, xmm13, xmm4 movdqu xmmword ptr [rsp + 0x2c0], xmm4 vcmpltps xmm11, xmm1, xmm12 vpblendvb xmm1, xmm1, xmm12, xmm11 movdqu xmmword ptr [rsp + 0x2b0], xmm11 vcmpltps xmm4, xmm1, xmm3 vpblendvb xmm1, xmm1, xmm3, xmm4 movdqu xmmword ptr [rsp + 0x2a0], xmm4 vcmpltps xmm13, xmm1, xmm2 vpblendvb xmm1, xmm1, xmm2, xmm13 movdqu xmmword ptr [rsp + 0x290], xmm13 vcmpltps xmm5, xmm1, xmm0 vpblendvb xmm1, xmm1, xmm0, xmm5 movdqu xmmword ptr [rsp + 0x280], xmm5 vcmpltps xmm4, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm4 movdqu xmm6, xmmword ptr [rsp + 0x20] movdqu xmmword ptr [rsp + 0x270], xmm4 vcmpltps xmm15, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm15 movdqu xmm5, xmmword ptr [rsp + 0x30] movdqu xmmword ptr [rsp + 0x260], xmm15 vcmpltps xmm6, xmm1, xmm5 vpblendvb xmm1, xmm1, xmm5, xmm6 movdqu xmm4, xmmword ptr [rsp + 0x40] movdqu xmmword ptr [rsp + 0x250], xmm6 vcmpltps xmm14, xmm1, xmm4 vpblendvb xmm1, xmm1, xmm4, xmm14 movdqu xmm7, xmmword ptr [rsp + 0x50] movdqu xmmword ptr [rsp + 0x240], xmm14 vcmpltps xmm14, xmm1, xmm7 vpblendvb xmm1, xmm1, xmm7, xmm14 movdqu xmm8, xmmword ptr [rsp + 0x60] movdqu xmmword ptr [rsp + 0x230], xmm14 vcmpltps xmm14, xmm1, xmm8 vpblendvb xmm1, xmm1, xmm8, xmm14 movdqu xmmword ptr [rsp + 0x220], xmm14 movdqu xmm14, xmmword ptr [rsp + 0x70] vcmpltps xmm2, xmm1, xmm14 vpblendvb xmm1, xmm1, xmm14, xmm2 movdqu xmm7, xmmword ptr [rsp + 0x80] movdqu xmmword ptr [rsp + 0x210], xmm2 vcmpltps xmm0, xmm1, xmm7 vpblendvb xmm1, xmm1, xmm7, xmm0 movdqu xmm4, xmmword ptr [rsp + 0x90] movdqu xmmword ptr [rsp + 0x200], xmm0 vcmpltps xmm9, xmm1, xmm4 vpblendvb xmm1, xmm1, xmm4, xmm9 movdqu xmm5, xmmword ptr [rsp + 0xa0] movdqu xmmword ptr [rsp + 0x1f0], xmm9 vcmpltps xmm10, xmm1, xmm5 vpblendvb xmm1, xmm1, xmm5, xmm10 movdqu xmm13, xmmword ptr [rsp + 0xb0] movdqu xmmword ptr [rsp + 0x1e0], xmm10 vcmpltps xmm2, xmm1, xmm13 vpblendvb xmm1, xmm1, xmm13, xmm2 movdqu xmm3, xmmword ptr [rsp + 0xc0] movdqu xmmword ptr [rsp + 0x1d0], xmm2 vcmpltps xmm12, xmm1, xmm3 vpblendvb xmm1, xmm1, xmm3, xmm12 movdqu xmm7, xmmword ptr [rsp + 0xd0] movdqu xmmword ptr [rsp + 0x1c0], xmm12 vcmpltps xmm11, xmm1, xmm7 vpblendvb xmm1, xmm1, xmm7, xmm11 movdqu xmm6, xmmword ptr [rsp + 0xe0] movdqu xmmword ptr [rsp + 0x1b0], xmm11 vcmpltps xmm3, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm3 movdqu xmm2, xmmword ptr [rsp + 0xf0] movdqu xmmword ptr [rsp + 0x1a0], xmm3 vcmpltps xmm13, xmm1, xmm2 vpblendvb xmm1, xmm1, xmm2, xmm13 movdqu xmm10, xmmword ptr [rsp + 0x100] movdqu xmmword ptr [rsp + 0x190], xmm13 vcmpltps xmm5, xmm1, xmm10 vpblendvb xmm1, xmm1, xmm10, xmm5 movdqu xmm9, xmmword ptr [rsp + 0x110] movdqu xmmword ptr [rsp + 0x180], xmm5 vcmpltps xmm4, xmm1, xmm9 vpblendvb xmm1, xmm1, xmm9, xmm4 movdqu xmm0, xmmword ptr [rsp + 0x120] movdqu xmmword ptr [rsp + 0x170], xmm4 vcmpltps xmm15, xmm1, xmm0 vpblendvb xmm1, xmm1, xmm0, xmm15 movdqu xmm8, xmmword ptr [rsp + 0x130] movdqu xmmword ptr [rsp + 0x160], xmm15 vcmpltps xmm6, xmm1, xmm8 vpblendvb xmm1, xmm1, xmm8, xmm6 movdqu xmmword ptr [rsp + 0x150], xmm6 movdqu xmm6, xmmword ptr [rsp + 0x350] vcmpltps xmm7, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm7 movdqu xmm6, xmmword ptr [rsp + 0x360] movdqu xmmword ptr [rsp + 0x140], xmm7 vcmpltps xmm8, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm8 movdqu xmm15, xmmword ptr [rsp + 0x370] movdqu xmmword ptr [rsp + 0x130], xmm8 vcmpltps xmm14, xmm1, xmm15 vpblendvb xmm1, xmm1, xmm15, xmm14 movdqu xmmword ptr [rsp + 0x120], xmm14 movdqu xmm14, xmmword ptr [rsp + 0x380] vcmpltps xmm2, xmm1, xmm14 vpblendvb xmm1, xmm1, xmm14, xmm2 movdqu xmm4, xmmword ptr [rsp + 0x390] movdqu xmmword ptr [rsp + 0x110], xmm2 vcmpltps xmm0, xmm1, xmm4 vpblendvb xmm1, xmm1, xmm4, xmm0 movdqu xmm5, xmmword ptr [rsp + 0x3a0] movdqu xmmword ptr [rsp + 0x100], xmm0 vcmpltps xmm9, xmm1, xmm5 vpblendvb xmm1, xmm1, xmm5, xmm9 movdqu xmm13, xmmword ptr [rsp + 0x3b0] movdqu xmmword ptr [rsp + 0xf0], xmm9 vcmpltps xmm10, xmm1, xmm13 vpblendvb xmm1, xmm1, xmm13, xmm10 movdqu xmm3, xmmword ptr [rsp + 0x3c0] movdqu xmmword ptr [rsp + 0xe0], xmm10 vcmpltps xmm2, xmm1, xmm3 vpblendvb xmm1, xmm1, xmm3, xmm2 movdqu xmm3, xmmword ptr [rsp + 0x3d0] movdqu xmmword ptr [rsp + 0xd0], xmm2 vcmpltps xmm12, xmm1, xmm3 vpblendvb xmm1, xmm1, xmm3, xmm12 movdqu xmm2, xmmword ptr [rsp + 0x3e0] movdqu xmmword ptr [rsp + 0xc0], xmm12 vcmpltps xmm11, xmm1, xmm2 vpblendvb xmm1, xmm1, xmm2, xmm11 movdqu xmm12, xmmword ptr [rsp + 0x3f0] movdqu xmmword ptr [rsp + 0xb0], xmm11 vcmpltps xmm3, xmm1, xmm12 vpblendvb xmm1, xmm1, xmm12, xmm3 movdqu xmm2, xmmword ptr [rsp + 0x400] movdqu xmmword ptr [rsp + 0xa0], xmm3 vcmpltps xmm13, xmm1, xmm2 vpblendvb xmm1, xmm1, xmm2, xmm13 movdqu xmm10, xmmword ptr [rsp + 0x410] movdqu xmmword ptr [rsp + 0x90], xmm13 vcmpltps xmm5, xmm1, xmm10 vpblendvb xmm1, xmm1, xmm10, xmm5 movdqu xmm9, xmmword ptr [rsp + 0x420] movdqu xmmword ptr [rsp + 0x80], xmm5 vcmpltps xmm4, xmm1, xmm9 vpblendvb xmm1, xmm1, xmm9, xmm4 movdqu xmm0, xmmword ptr [rsp + 0x430] movdqu xmmword ptr [rsp + 0x70], xmm4 vcmpltps xmm15, xmm1, xmm0 vpblendvb xmm1, xmm1, xmm0, xmm15 movdqu xmm8, xmmword ptr [rsp + 0x440] movdqu xmmword ptr [rsp + 0x60], xmm15 vcmpltps xmm6, xmm1, xmm8 vpblendvb xmm1, xmm1, xmm8, xmm6 movdqu xmm2, xmmword ptr [rsp + 0x450] movdqu xmmword ptr [rsp + 0x50], xmm6 vcmpltps xmm7, xmm1, xmm2 vpblendvb xmm1, xmm1, xmm2, xmm7 movdqu xmm6, xmmword ptr [rsp + 0x460] movdqu xmmword ptr [rsp + 0x40], xmm7 vcmpltps xmm8, xmm1, xmm6 vpblendvb xmm1, xmm1, xmm6, xmm8 movdqu xmm15, xmmword ptr [rsp + 0x470] movdqu xmmword ptr [rsp + 0x30], xmm8 vcmpltps xmm14, xmm1, xmm15 vpblendvb xmm1, xmm1, xmm15, xmm14 movdqu xmm4, xmmword ptr [rsp + 0x480] movdqu xmmword ptr [rsp + 0x20], xmm14 vcmpltps xmm14, xmm1, xmm4 vpblendvb xmm2, xmm1, xmm4, xmm14 movdqu xmm5, xmmword ptr [rsp + 0x490] vcmpltps xmm1, xmm2, xmm5 vpblendvb xmm2, xmm2, xmm5, xmm1 movdqu xmm13, xmmword ptr [rsp + 0x4a0] vcmpltps xmm0, xmm2, xmm13 vpblendvb xmm2, xmm2, xmm13, xmm0 movdqu xmm3, xmmword ptr [rsp + 0x4b0] vcmpltps xmm9, xmm2, xmm3 vpblendvb xmm2, xmm2, xmm3, xmm9 movdqu xmm5, xmmword ptr [rsp + 0x4c0] vcmpltps xmm10, xmm2, xmm5 vpblendvb xmm3, xmm2, xmm5, xmm10 movdqu xmm11, xmmword ptr [rsp + 0x4d0] vcmpltps xmm2, xmm3, xmm11 vpblendvb xmm3, xmm3, xmm11, xmm2 movdqu xmm4, xmmword ptr [rsp + 0x4e0] vcmpltps xmm12, xmm3, xmm4 vpblendvb xmm3, xmm3, xmm4, xmm12 movdqu xmm4, xmmword ptr [rsp + 0x4f0] vcmpltps xmm11, xmm3, xmm4 vpblendvb xmm4, xmm3, xmm4, xmm11 movdqu xmm5, xmmword ptr [rsp + 0x500] vcmpltps xmm3, xmm4, xmm5 vpblendvb xmm4, xmm4, xmm5, xmm3 movdqu xmm7, xmmword ptr [rsp + 0x510] vcmpltps xmm13, xmm4, xmm7 vpblendvb xmm5, xmm4, xmm7, xmm13 movdqu xmm6, xmmword ptr [rsp + 0x520] vcmpltps xmm4, xmm5, xmm6 vpblendvb xmm5, xmm5, xmm6, xmm4 movdqu xmm7, xmmword ptr [rsp + 0x530] vcmpltps xmm15, xmm5, xmm7 movdqu xmm8, xmmword ptr [rsp + 0x340] movdqu xmm7, xmmword ptr [rsp + 0x920] movdqu xmm6, xmmword ptr [rsp] vpblendvb xmm6, xmm6, xmm7, xmm8 movdqu xmm7, xmmword ptr [rsp + 0x330] movdqu xmm8, xmmword ptr [rsp + 0x540] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x320] movdqu xmm8, xmmword ptr [rsp + 0x550] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x310] movdqu xmm8, xmmword ptr [rsp + 0x560] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x300] movdqu xmm8, xmmword ptr [rsp + 0x570] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2f0] movdqu xmm8, xmmword ptr [rsp + 0x580] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2e0] movdqu xmm8, xmmword ptr [rsp + 0x590] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2d0] movdqu xmm8, xmmword ptr [rsp + 0x5a0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2c0] movdqu xmm8, xmmword ptr [rsp + 0x5b0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2b0] movdqu xmm8, xmmword ptr [rsp + 0x5c0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2a0] movdqu xmm8, xmmword ptr [rsp + 0x5d0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x290] movdqu xmm8, xmmword ptr [rsp + 0x5e0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x280] movdqu xmm8, xmmword ptr [rsp + 0x5f0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x270] movdqu xmm8, xmmword ptr [rsp + 0x600] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x260] movdqu xmm8, xmmword ptr [rsp + 0x610] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x250] movdqu xmm8, xmmword ptr [rsp + 0x620] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x240] movdqu xmm8, xmmword ptr [rsp + 0x630] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x230] movdqu xmm8, xmmword ptr [rsp + 0x640] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x220] movdqu xmm8, xmmword ptr [rsp + 0x650] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x210] movdqu xmm8, xmmword ptr [rsp + 0x660] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x200] movdqu xmm8, xmmword ptr [rsp + 0x670] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1f0] movdqu xmm8, xmmword ptr [rsp + 0x680] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1e0] movdqu xmm8, xmmword ptr [rsp + 0x690] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1d0] movdqu xmm8, xmmword ptr [rsp + 0x6a0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1c0] movdqu xmm8, xmmword ptr [rsp + 0x6b0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1b0] movdqu xmm8, xmmword ptr [rsp + 0x6c0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x1a0] movdqu xmm8, xmmword ptr [rsp + 0x6d0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x190] movdqu xmm8, xmmword ptr [rsp + 0x6e0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x180] movdqu xmm8, xmmword ptr [rsp + 0x6f0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x170] movdqu xmm8, xmmword ptr [rsp + 0x700] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x160] movdqu xmm8, xmmword ptr [rsp + 0x710] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x150] movdqu xmm8, xmmword ptr [rsp + 0x720] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x140] movdqu xmm8, xmmword ptr [rsp + 0x730] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x130] movdqu xmm8, xmmword ptr [rsp + 0x740] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x120] movdqu xmm8, xmmword ptr [rsp + 0x750] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x110] movdqu xmm8, xmmword ptr [rsp + 0x760] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x100] movdqu xmm8, xmmword ptr [rsp + 0x770] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xf0] movdqu xmm8, xmmword ptr [rsp + 0x780] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xe0] movdqu xmm8, xmmword ptr [rsp + 0x790] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xd0] movdqu xmm8, xmmword ptr [rsp + 0x7a0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xc0] movdqu xmm8, xmmword ptr [rsp + 0x7b0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xb0] movdqu xmm8, xmmword ptr [rsp + 0x7c0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0xa0] movdqu xmm8, xmmword ptr [rsp + 0x7d0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x90] movdqu xmm8, xmmword ptr [rsp + 0x7e0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x80] movdqu xmm8, xmmword ptr [rsp + 0x7f0] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x70] movdqu xmm8, xmmword ptr [rsp + 0x800] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x60] movdqu xmm8, xmmword ptr [rsp + 0x810] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x50] movdqu xmm8, xmmword ptr [rsp + 0x820] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x40] movdqu xmm8, xmmword ptr [rsp + 0x830] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x30] movdqu xmm8, xmmword ptr [rsp + 0x840] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x20] movdqu xmm8, xmmword ptr [rsp + 0x850] vpblendvb xmm6, xmm6, xmm8, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x860] vpblendvb xmm6, xmm6, xmm7, xmm14 movdqu xmm7, xmmword ptr [rsp + 0x870] vpblendvb xmm1, xmm6, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x880] vpblendvb xmm1, xmm1, xmm7, xmm0 movdqu xmm6, xmmword ptr [rsp + 0x890] vpblendvb xmm1, xmm1, xmm6, xmm9 movdqu xmm7, xmmword ptr [rsp + 0x8a0] vpblendvb xmm1, xmm1, xmm7, xmm10 movdqu xmm6, xmmword ptr [rsp + 0x8b0] vpblendvb xmm1, xmm1, xmm6, xmm2 movdqu xmm10, xmmword ptr [rsp + 0x8c0] vpblendvb xmm1, xmm1, xmm10, xmm12 movdqu xmm0, xmmword ptr [rsp + 0x8d0] vpblendvb xmm1, xmm1, xmm0, xmm11 movdqu xmm7, xmmword ptr [rsp + 0x8e0] vpblendvb xmm1, xmm1, xmm7, xmm3 movdqu xmm8, xmmword ptr [rsp + 0x8f0] vpblendvb xmm1, xmm1, xmm8, xmm13 movdqu xmm3, xmmword ptr [rsp + 0x900] vpblendvb xmm1, xmm1, xmm3, xmm4 movdqu xmm4, xmmword ptr [rsp + 0x910] vpblendvb xmm6, xmm1, xmm4, xmm15 movdqu xmm4, xmmword ptr [rsp + 0x530] vpblendvb xmm8, xmm5, xmm4, xmm15 add r11d, 0xfc movdqu xmmword ptr [rsp], xmm6 movdqu xmmword ptr [rsp + 0x11], xmm8 jmp lbl41 movdqu xmm6, xmmword ptr [rsp] movdqu xmm7, xmmword ptr [rsp + 0x920] movdqu xmm8, xmmword ptr [rsp + 0x10] vpcmpeqd xmm2, xmm0, xmm0 vpsrld xmm4, xmm2, 0x1 vandps xmm1, xmm7, xmm4 vcmpltps xmm0, xmm8, xmm1 vpblendvb xmm4, xmm8, xmm1, xmm0 vpshufd xmm3, xmm4, 0x3 # xmm3 = xmm4[3,0,0,0] vpshufd xmm5, xmm4, 0x2 # xmm5 = xmm4[2,0,0,0] vpshufd xmm1, xmm4, 0x1 # xmm1 = xmm4[1,0,0,0] vucomiss xmm1, xmm4 movdqa xmm2, xmm4 jbe lbll1971 movsd xmm2, xmm1 # xmm2 = xmm1[0],xmm2[1] vucomiss xmm5, xmm2 movdqa xmm13, xmm2 jbe lbll1985 movsd xmm13, xmm5 # xmm13 = xmm5[0],xmm13[1] vpblendvb xmm0, xmm6, xmm7, xmm0 vpshufd xmm6, xmm0, 0x3 # xmm6 = xmm0[3,0,0,0] vpshufd xmm7, xmm0, 0x2 # xmm7 = xmm0[2,0,0,0] vpshufd xmm14, xmm0, 0x1 # xmm14 = xmm0[1,0,0,0] vucomiss xmm1, xmm4 jbe lbll19a9 movsd xmm0, xmm14 # xmm0 = xmm14[0],xmm0[1] vucomiss xmm5, xmm2 jbe lbll19b7 movsd xmm0, xmm7 # xmm0 = xmm7[0],xmm0[1] vucomiss xmm3, xmm13 jbe lbll19c6 movsd xmm0, xmm6 # xmm0 = xmm6[0],xmm0[1] add rsp, 0x930 mov rsp, rbp pop rbp ret
analysis source #3
Output
Compile to binary object
Link to binary
Execute the code
Intel asm syntax
Demangle identifiers
Verbose demangling
Filters
Unused labels
Library functions
Directives
Comments
Horizontal whitespace
Debug intrinsics
Compiler
OSACA (0.7.1)
llvm-mca (assertions trunk)
llvm-mca (trunk)
Options
Source code
abs_max_val_camel: push rbp mov rbp, rsp mov r10, qword ptr [rdi + 0x8] mov r10, qword ptr [r10] add r10, 0x350 cmp r10, rsp ja lbl sub rsp, 0x350 mov rsi, qword ptr [rdi + 0x58] mov rsi, qword ptr [rsi] mov eax, edx vmovdqu xmm1, xmmword ptr [rsi + rax] movdqu xmmword ptr [rsp + 0x340], xmm1 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x10] movdqu xmmword ptr [rsp + 0x330], xmm7 vmovdqu xmm2, xmmword ptr [rsi + rax + 0x20] vmovdqu xmm3, xmmword ptr [rsi + rax + 0x30] vmovdqu xmm4, xmmword ptr [rsi + rax + 0x40] movdqa xmm1, xmm4 vmovdqu xmm5, xmmword ptr [rsi + rax + 0x50] vmovdqu xmm6, xmmword ptr [rsi + rax + 0x60] movdqu xmmword ptr [rsp + 0x320], xmm6 vmovdqu xmm15, xmmword ptr [rsi + rax + 0x70] vmovdqu xmm8, xmmword ptr [rsi + rax + 0x80] vmovdqu xmm9, xmmword ptr [rsi + rax + 0x90] vmovdqu xmm10, xmmword ptr [rsi + rax + 0xa0] vmovdqu xmm11, xmmword ptr [rsi + rax + 0xb0] vmovdqu xmm12, xmmword ptr [rsi + rax + 0xc0] vmovdqu xmm13, xmmword ptr [rsi + rax + 0xd0] vmovdqu xmm14, xmmword ptr [rsi + rax + 0xe0] movdqu xmmword ptr [rsp + 0x310], xmm14 vmovdqu xmm14, xmmword ptr [rsi + rax + 0xf0] movdqu xmmword ptr [rsp + 0x300], xmm14 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x100] movdqu xmmword ptr [rsp + 0x2f0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x110] movdqu xmmword ptr [rsp + 0x2e0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x120] movdqu xmmword ptr [rsp + 0x2d0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x130] movdqu xmmword ptr [rsp + 0x2c0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x140] movdqu xmmword ptr [rsp + 0x2b0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x150] movdqu xmmword ptr [rsp + 0x2a0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x160] movdqu xmmword ptr [rsp + 0x290], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x170] movdqu xmmword ptr [rsp + 0x280], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x180] movdqu xmmword ptr [rsp + 0x270], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x190] movdqu xmmword ptr [rsp + 0x260], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1a0] movdqu xmmword ptr [rsp + 0x250], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1b0] movdqu xmmword ptr [rsp + 0x240], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1c0] movdqu xmmword ptr [rsp + 0x230], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1d0] movdqu xmmword ptr [rsp + 0x220], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1e0] movdqu xmmword ptr [rsp + 0x210], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x1f0] movdqu xmmword ptr [rsp + 0x200], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x200] movdqu xmmword ptr [rsp + 0x1f0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x210] movdqu xmmword ptr [rsp + 0x1e0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x220] movdqu xmmword ptr [rsp + 0x1d0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x230] movdqu xmmword ptr [rsp + 0x1c0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x240] movdqu xmmword ptr [rsp + 0x1b0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x250] movdqu xmmword ptr [rsp + 0x1a0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x260] movdqu xmmword ptr [rsp + 0x190], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x270] movdqu xmmword ptr [rsp + 0x180], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x280] movdqu xmmword ptr [rsp + 0x170], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x290] movdqu xmmword ptr [rsp + 0x160], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2a0] movdqu xmmword ptr [rsp + 0x150], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2b0] movdqu xmmword ptr [rsp + 0x140], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2c0] movdqu xmmword ptr [rsp + 0x130], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2d0] movdqu xmmword ptr [rsp + 0x120], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2e0] movdqu xmmword ptr [rsp + 0x110], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x2f0] movdqu xmmword ptr [rsp + 0x100], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x300] movdqu xmmword ptr [rsp + 0xf0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x310] movdqu xmmword ptr [rsp + 0xe0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x320] movdqu xmmword ptr [rsp + 0xd0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x330] movdqu xmmword ptr [rsp + 0xc0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x340] movdqu xmmword ptr [rsp + 0xb0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x350] movdqu xmmword ptr [rsp + 0xa0], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x360] movdqu xmmword ptr [rsp + 0x90], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x370] movdqu xmmword ptr [rsp + 0x80], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x380] movdqu xmmword ptr [rsp + 0x70], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x390] movdqu xmmword ptr [rsp + 0x60], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3a0] movdqu xmmword ptr [rsp + 0x50], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3b0] movdqu xmmword ptr [rsp + 0x40], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3c0] movdqu xmmword ptr [rsp + 0x30], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3d0] movdqu xmmword ptr [rsp + 0x20], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3e0] movdqu xmmword ptr [rsp + 0x10], xmm7 vmovdqu xmm7, xmmword ptr [rsi + rax + 0x3f0] movdqu xmmword ptr [rsp], xmm7 movdqu xmm4, xmmword ptr [rsp + 0x330] movdqu xmm6, xmmword ptr [rsp + 0x340] vmaxps xmm0, xmm4, xmm6 vmaxps xmm0, xmm2, xmm0 vmaxps xmm0, xmm3, xmm0 movdqa xmm4, xmm1 vmaxps xmm0, xmm4, xmm0 vmaxps xmm0, xmm5, xmm0 movdqu xmm6, xmmword ptr [rsp + 0x320] vmaxps xmm0, xmm6, xmm0 vmaxps xmm0, xmm15, xmm0 vmaxps xmm0, xmm8, xmm0 vmaxps xmm0, xmm9, xmm0 vmaxps xmm0, xmm10, xmm0 vmaxps xmm0, xmm11, xmm0 vmaxps xmm0, xmm12, xmm0 vmaxps xmm0, xmm13, xmm0 movdqu xmm14, xmmword ptr [rsp + 0x310] vmaxps xmm7, xmm14, xmm0 movdqu xmm0, xmmword ptr [rsp + 0x300] vmaxps xmm1, xmm0, xmm7 movdqu xmm7, xmmword ptr [rsp + 0x2f0] vmaxps xmm0, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2e0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x2d0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x2c0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x2b0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x2a0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x290] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x280] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x270] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x260] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x250] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x240] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x230] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x220] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x210] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x200] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1f0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1e0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1d0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1c0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1b0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x1a0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x190] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x180] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x170] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x160] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x150] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x140] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x130] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x120] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x110] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x100] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xf0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xe0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xd0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xc0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xb0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0xa0] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x90] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x80] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x70] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x60] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x50] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x40] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x30] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x20] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp + 0x10] vmaxps xmm0, xmm7, xmm0 movdqu xmm7, xmmword ptr [rsp] vmaxps xmm0, xmm7, xmm0 vpshufd xmm1, xmm0, 0x4e # xmm1 = xmm0[2,3,0,1] vmaxps xmm0, xmm1, xmm0 vpshufd xmm1, xmm0, 0xb1 # xmm1 = xmm0[1,0,3,2] vmaxps xmm0, xmm1, xmm0 movdqu xmm1, xmmword ptr [rsp + 0x340] movdqu xmm7, xmmword ptr [rsp + 0x330] vminps xmm1, xmm7, xmm1 vminps xmm1, xmm2, xmm1 vminps xmm1, xmm3, xmm1 vminps xmm1, xmm4, xmm1 vminps xmm1, xmm5, xmm1 vminps xmm1, xmm6, xmm1 vminps xmm1, xmm15, xmm1 vminps xmm1, xmm8, xmm1 vminps xmm1, xmm9, xmm1 vminps xmm1, xmm10, xmm1 vminps xmm1, xmm11, xmm1 vminps xmm1, xmm12, xmm1 vminps xmm1, xmm13, xmm1 vminps xmm1, xmm14, xmm1 movdqu xmm14, xmmword ptr [rsp + 0x300] vminps xmm1, xmm14, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2f0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2e0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2d0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2c0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2b0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x2a0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x290] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x280] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x270] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x260] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x250] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x240] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x230] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x220] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x210] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x200] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1f0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1e0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1d0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1c0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1b0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x1a0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x190] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x180] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x170] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x160] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x150] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x140] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x130] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x120] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x110] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x100] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xf0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xe0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xd0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xc0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xb0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0xa0] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x90] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x80] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x70] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x60] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x50] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x40] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x30] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x20] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp + 0x10] vminps xmm1, xmm7, xmm1 movdqu xmm7, xmmword ptr [rsp] vminps xmm1, xmm7, xmm1 vpshufd xmm2, xmm1, 0x4e # xmm2 = xmm1[2,3,0,1] vminps xmm1, xmm2, xmm1 vpshufd xmm2, xmm1, 0xb1 # xmm2 = xmm1[1,0,3,2] vminps xmm1, xmm2, xmm1 mov r11d, 0x80000000 vmovd xmm2, r11d vxorps xmm2, xmm1, xmm2 vucomiss xmm2, xmm0 jbe lbl2 movsd xmm0, xmm1 # xmm0 = xmm1[0],xmm0[1] add rsp, 0x350 mov rsp, rbp pop rbp ret
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