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/**
 * \file
 *
 * \brief I2C master driver.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

#ifndef I2C_TYPES_H
#define I2C_TYPES_H

#include <stdint.h>

typedef enum {
	I2C_NOERR, // The message was sent.
	I2C_BUSY,  // Message was NOT sent, bus was busy.
	I2C_FAIL   // Message was NOT sent, bus failure
	           // If you are interested in the failure reason,
	           // Sit on the event call-backs.
} i2c_error_t;

typedef enum { i2c_stop = 1, i2c_restart_read, i2c_restart_write, i2c_continue, i2c_reset_link } i2c_operations_t;

typedef i2c_operations_t (*i2c_callback)(void *p);

typedef uint8_t i2c_address_t;

// common callback responses
i2c_operations_t i2c_cb_return_stop(void *p);
i2c_operations_t i2c_cb_return_reset(void *p);
i2c_operations_t i2c_cb_restart_write(void *p);
i2c_operations_t i2c_cb_restart_read(void *p);

#endif /* I2C_TYPES_H */

/**
 * \file
 *
 * \brief I2C Simple master driver.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

#ifndef I2C_SIMPLE_MASTER_H
#define I2C_SIMPLE_MASTER_H

#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
// #include <i2c_types.h>

#ifdef __cplusplus
extern "C" {
#endif

#define I2C_TIMEOUT 10000

#define TWI0_BAUD(F_SCL, T_RISE) ((((((float)3333333 / (float)F_SCL)) - 10 - ((float)3333333 * T_RISE / 1000000))) / 2)

uint8_t     I2C_0_read1ByteRegister(i2c_address_t address, uint8_t reg);
uint16_t    I2C_0_read2ByteRegister(i2c_address_t address, uint8_t reg);
i2c_error_t I2C_0_write1ByteRegister(i2c_address_t address, uint8_t reg, uint8_t data);
i2c_error_t I2C_0_write2ByteRegister(i2c_address_t address, uint8_t reg, uint16_t data);

i2c_error_t I2C_0_writeNBytes(i2c_address_t address, void *data, size_t len);
i2c_error_t I2C_0_readDataBlock(i2c_address_t address, uint8_t reg, void *data, size_t len);
i2c_error_t I2C_0_readNBytes(i2c_address_t address, void *data, size_t len);

#ifdef __cplusplus
}
#endif

#endif /* I2C_SIMPLE_MASTER_H_INCLUDED */

/**
 * \file
 *
 * \brief I2C master driver.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

#ifndef I2C_MASTER_H
#define I2C_MASTER_H

#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
// #include <i2c_types.h>

#ifdef __cplusplus
extern "C" {
#endif

#define TWI0_BAUD(F_SCL, T_RISE) ((((((float)3333333 / (float)F_SCL)) - 10 - ((float)3333333 * T_RISE / 1000000))) / 2)

void I2C_0_init(void);

i2c_error_t I2C_0_open(i2c_address_t address);

i2c_error_t I2C_0_close(void);

i2c_error_t I2C_0_master_operation(bool read);

i2c_error_t I2C_0_master_write(void); // to be depreciated

i2c_error_t I2C_0_master_read(void); // to be depreciated

void I2C_0_set_timeout(uint8_t to);

void I2C_0_set_baud_rate(uint32_t baud);

void I2C_0_set_buffer(void *buffer, size_t bufferSize);

// Event Callback functions.

void I2C_0_set_data_complete_callback(i2c_callback cb, void *p);

void I2C_0_set_write_collision_callback(i2c_callback cb, void *p);

void I2C_0_set_address_nack_callback(i2c_callback cb, void *p);

void I2C_0_set_data_nack_callback(i2c_callback cb, void *p);

void I2C_0_set_timeout_callback(i2c_callback cb, void *p);

#ifdef __cplusplus
}
#endif

#endif /* I2C_MASTER_H_INCLUDED */

/**
 * \file
 *
 * \brief I2C master driver types.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

// #include "i2c_types.h"

i2c_operations_t i2c_cb_return_stop(void *p)
{
	return i2c_stop;
}

i2c_operations_t i2c_cb_return_reset(void *p)
{
	return i2c_reset_link;
}

i2c_operations_t i2c_cb_restart_write(void *p)
{
	return i2c_restart_write;
}

i2c_operations_t i2c_cb_restart_read(void *p)
{
	return i2c_restart_read;
}

/**
 * \file
 *
 * \brief I2C Simple master driver.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

/**
 * \defgroup doc_driver_i2c_simple_master I2C Simple Master Driver
 * \ingroup doc_driver_i2c
 *
 * \section doc_driver_i2c_simple_master_rev Revision History
 * - v0.0.0.1 Initial Commit
 *
 *@{
 */

// #include <i2c_master.h>
// #include <i2c_simple_master.h>

static i2c_operations_t I2C_0_wr1RegCompleteHandler(void *p)
{
	I2C_0_set_buffer(p, 1);
	I2C_0_set_data_complete_callback(NULL, NULL);
	return i2c_continue;
}

i2c_error_t I2C_0_write1ByteRegister(i2c_address_t address, uint8_t reg, uint8_t data)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t timeout = I2C_TIMEOUT;

while (I2C_BUSY == I2C_0_open(address) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;
	I2C_0_set_data_complete_callback(I2C_0_wr1RegCompleteHandler, &data);
	I2C_0_set_buffer(&reg, 1);
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
	I2C_0_master_write();
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

i2c_error_t I2C_0_writeNBytes(i2c_address_t address, void *data, size_t len)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t timeout = I2C_TIMEOUT;

while (I2C_BUSY == I2C_0_open(address) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;
	I2C_0_set_buffer(data, len);
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
	I2C_0_master_write();
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

static i2c_operations_t I2C_0_rd1RegCompleteHandler(void *p)
{
	I2C_0_set_buffer(p, 1);
	I2C_0_set_data_complete_callback(NULL, NULL);
	return i2c_restart_read;
}

uint8_t I2C_0_read1ByteRegister(i2c_address_t address, uint8_t reg)
{
	uint8_t     d2 = 42;
	i2c_error_t e;
	int         x;

for (x = 2; x != 0; x--) {
		while (!I2C_0_open(address))
			; // sit here until we get the bus..
		I2C_0_set_data_complete_callback(I2C_0_rd1RegCompleteHandler, &d2);
		I2C_0_set_buffer(&reg, 1);
		I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
		I2C_0_master_write();
		while (I2C_BUSY == (e = I2C_0_close()))
			; // sit here until finished.
		if (e == I2C_NOERR)
			break;
	}

return d2;
}

static i2c_operations_t I2C_0_rd2RegCompleteHandler(void *p)
{
	I2C_0_set_buffer(p, 2);
	I2C_0_set_data_complete_callback(NULL, NULL);
	return i2c_restart_read;
}

uint16_t I2C_0_read2ByteRegister(i2c_address_t address, uint8_t reg)
{
	// result is little endian
	uint16_t result;

while (!I2C_0_open(address))
		; // sit here until we get the bus..
	I2C_0_set_data_complete_callback(I2C_0_rd2RegCompleteHandler, &result);
	I2C_0_set_buffer(&reg, 1);
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
	I2C_0_master_write();
	while (I2C_BUSY == I2C_0_close())
		; // sit here until finished.

return (result << 8 | result >> 8);
}

/****************************************************************/
static i2c_operations_t I2C_0_wr2RegCompleteHandler(void *p)
{
	I2C_0_set_buffer(p, 2);
	I2C_0_set_data_complete_callback(NULL, NULL);
	return i2c_continue;
}

i2c_error_t I2C_0_write2ByteRegister(i2c_address_t address, uint8_t reg, uint16_t data)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t timeout = I2C_TIMEOUT;

while (I2C_BUSY == I2C_0_open(address) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;
	I2C_0_set_data_complete_callback(I2C_0_wr2RegCompleteHandler, &data);
	I2C_0_set_buffer(&reg, 1);
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
	I2C_0_master_write();
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

/****************************************************************/
typedef struct {
	size_t len;
	char * data;
} I2C_0_buf_t;

static i2c_operations_t I2C_0_rdBlkRegCompleteHandler(void *p)
{
	I2C_0_set_buffer(((I2C_0_buf_t *)p)->data, ((I2C_0_buf_t *)p)->len);
	I2C_0_set_data_complete_callback(NULL, NULL);
	return i2c_restart_read;
}

i2c_error_t I2C_0_readDataBlock(i2c_address_t address, uint8_t reg, void *data, size_t len)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t timeout = I2C_TIMEOUT;
	// result is little endian
	I2C_0_buf_t d;
//d.data = data;
d.data = (char*)data;
	d.len  = len;

while (I2C_BUSY == I2C_0_open(address) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;
	I2C_0_set_data_complete_callback(I2C_0_rdBlkRegCompleteHandler, &d);
	I2C_0_set_buffer(&reg, 1);
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL); // NACK polling?
	I2C_0_master_write();
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

i2c_error_t I2C_0_readNBytes(i2c_address_t address, void *data, size_t len)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t timeout = I2C_TIMEOUT;

while (I2C_BUSY == I2C_0_open(address) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;
	I2C_0_set_buffer(data, len);
	I2C_0_master_read();
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

/**
 * \file
 *
 * \brief I2C master driver.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

/**
 * \defgroup doc_driver_i2c_master I2C Master Driver
 * \ingroup doc_driver_i2c
 *
 * \section doc_driver_i2c_master_rev Revision History
 * - v0.0.0.1 Initial Commit
 *
 *@{
 */

#include <avr/io.h>
// #include <i2c_master.h>
// #include <i2c_types.h>
// #include <driver_init.h>
#define F_CPU 3333333ul
#include <util/delay.h>
#include <stdbool.h>
#include <stdlib.h>
// #include "timeout.h"  // TODO: Add timeout integration

/***************************************************************************/
// I2C STATES
typedef enum {
	I2C_IDLE = 0,
	I2C_SEND_ADR_READ,
	I2C_SEND_ADR_WRITE,
	I2C_TX,
	I2C_RX,
	I2C_TX_EMPTY,
	I2C_SEND_RESTART_READ,
	I2C_SEND_RESTART_WRITE,
	I2C_SEND_RESTART,
	I2C_SEND_STOP,
	I2C_RX_DO_ACK,
	I2C_TX_DO_ACK,
	I2C_RX_DO_NACK_STOP,
	I2C_RX_DO_NACK_RESTART,
	I2C_RESET,
	I2C_ADDRESS_NACK,
	I2C_BUS_COLLISION,
	I2C_BUS_ERROR
} i2c_fsm_states_t;

// I2C Event Callback List
typedef enum {
	i2c_dataComplete = 0,
	i2c_writeCollision,
	i2c_addressNACK,
	i2c_dataNACK,
	i2c_timeOut,
	i2c_NULL
} i2c_callback_index;

// I2C Status Structure
typedef struct {
	unsigned         busy : 1;
	unsigned         inUse : 1;
	unsigned         bufferFree : 1;
	unsigned         addressNACKCheck : 1;
	i2c_address_t    address;       /// The I2C Address
	uint8_t *        data_ptr;      /// pointer to a data buffer
	size_t           data_length;   /// Bytes in the data buffer
	uint16_t         timeout;       /// I2C Timeout Counter between I2C Events.
	uint16_t         timeout_value; /// Reload value for the timeouts
	i2c_fsm_states_t state;         /// Driver State
	i2c_error_t      error;
	/*if timeoutDriverEnabled
	timerStruct_t timeout;
	*/
	i2c_callback callbackTable[6];
	void *       callbackPayload[6]; ///  each callback can have a payload
} i2c_status_t;

typedef i2c_fsm_states_t(stateHandlerFunction)(void);

i2c_status_t I2C_0_status = {0};

static void             I2C_0_set_callback(i2c_callback_index idx, i2c_callback cb, void *p);
static i2c_operations_t I2C_0_return_stop(void *p);
static i2c_operations_t I2C_0_return_reset(void *p);
static i2c_fsm_states_t I2C_0_do_I2C_SEND_ADR_READ(void);
static i2c_fsm_states_t I2C_0_do_I2C_SEND_ADR_WRITE(void);
static void             I2C_0_master_isr(void);

/*if timeoutDriverEnabled>
ABSOLUTETIME_t ${i2cMasterFunctions["timeoutHandler"]}(void *p);

// place this function someplace in a periodic interrupt
ABSOLUTETIME_t ${i2cMasterFunctions["timeoutHandler"]}(void *p)
{
    ${msspI2cFunctions["disableIRQ"]}();
    ${i2cMasterFunctions["status"]}.state = I2C_RESET; // Jump to the Timeout state
    ${msspI2cFunctions["enableIRQ"]}();
    ${msspI2cFunctions["setIRQ"]}(); // force an interrupt to handle the timeout
    return 0;
}
*/
/**
 * \brief Set callback to be called when all specifed data has been transferred.
 *
 * \param[in] cb Pointer to callback function
 * \param[in] p  Pointer to the callback function's parameters
 *
 * \return Nothing
 */
void I2C_0_set_data_complete_callback(i2c_callback cb, void *p)
{
	I2C_0_set_callback(i2c_dataComplete, cb, p);
}

/**
 * \brief Set callback to be called when there has been a bus collision and arbitration was lost.
 *
 * \param[in] cb Pointer to callback function
 * \param[in] p  Pointer to the callback function's parameters
 *
 * \return Nothing
 */
void I2C_0_set_write_collision_callback(i2c_callback cb, void *p)
{
	I2C_0_set_callback(i2c_writeCollision, cb, p);
}

/**
 * \brief Set callback to be called when the transmitted address was NACK'ed.
 *
 * \param[in] cb Pointer to callback function
 * \param[in] p  Pointer to the callback function's parameters
 *
 * \return Nothing
 */
void I2C_0_set_address_nack_callback(i2c_callback cb, void *p)
{
	I2C_0_set_callback(i2c_addressNACK, cb, p);
}

/**
 * \brief Set callback to be called when the transmitted data was NACK'ed.
 *
 * \param[in] cb Pointer to callback function
 * \param[in] p  Pointer to the callback function's parameters
 *
 * \return Nothing
 */
void I2C_0_set_data_nack_callback(i2c_callback cb, void *p)
{
	I2C_0_set_callback(i2c_dataNACK, cb, p);
}

/**
 * \brief Set callback to be called when there was a bus timeout.
 *
 * \param[in] cb Pointer to callback function
 * \param[in] p  Pointer to the callback function's parameters
 *
 * \return Nothing
 */
void I2C_0_set_timeout_callback(i2c_callback cb, void *p)
{
	I2C_0_set_callback(i2c_timeOut, cb, p);
}

/**
 * \brief Initialize I2C interface
 * If module is configured to disabled state, the clock to the I2C is disabled
 * if this is supported by the device's clock system.
 *
 * \return Initialization status.
 * \retval 0 the init was successful
 * \retval 1 the init was not successful
 */
void I2C_0_init()
{

// TWI0.CTRLA = 0 << TWI_FMPEN_bp /* FM Plus Enable: disabled */
	//		 | TWI_SDAHOLD_OFF_gc /* SDA hold time off */
	//		 | TWI_SDASETUP_4CYC_gc; /* SDA setup time is 4 clock cycles */

// TWI0.DBGCTRL = 0 << TWI_DBGRUN_bp; /* Debug Run: disabled */

TWI0.MBAUD = (uint8_t)TWI0_BAUD(100000, 0); /* set MBAUD register */

TWI0.MCTRLA = 1 << TWI_ENABLE_bp        /* Enable TWI Master: enabled */
	              | 0 << TWI_QCEN_bp        /* Quick Command Enable: disabled */
	              | 1 << TWI_RIEN_bp        /* Read Interrupt Enable: enabled */
	              | 0 << TWI_SMEN_bp        /* Smart Mode Enable: disabled */
	              | TWI_TIMEOUT_DISABLED_gc /* Bus Timeout Disabled */
	              | 1 << TWI_WIEN_bp;       /* Write Interrupt Enable: enabled */
}

/**
 * \brief Open the I2C for communication
 *
 * \param[in] address The slave address to use in the transfer
 *
 * \return Initialization status.
 * \retval I2C_NOERR The I2C open was successful
 * \retval I2C_BUSY  The I2C open failed because the interface is busy
 * \retval I2C_FAIL  The I2C open failed with an error
 */
i2c_error_t I2C_0_open(i2c_address_t address)
{
	i2c_error_t ret = I2C_BUSY;

if (!I2C_0_status.inUse) {
		I2C_0_status.address          = address;
		I2C_0_status.busy             = 0;
		I2C_0_status.inUse            = 1;
		I2C_0_status.addressNACKCheck = 0;
		I2C_0_status.state            = I2C_RESET;
		I2C_0_status.timeout_value    = 500; // MCC should determine a reasonable starting value here.
		I2C_0_status.bufferFree       = 1;
		/*
		        <#if timeoutDriverEnabled>
		        I2C_0_status.timeout.callbackPtr = ${i2cMasterFunctions["timeoutHandler"]};
		        </#if>
		*/
		// set all the call backs to a default of sending stop
		I2C_0_status.callbackTable[i2c_dataComplete]     = I2C_0_return_stop;
		I2C_0_status.callbackPayload[i2c_dataComplete]   = NULL;
		I2C_0_status.callbackTable[i2c_writeCollision]   = I2C_0_return_stop;
		I2C_0_status.callbackPayload[i2c_writeCollision] = NULL;
		I2C_0_status.callbackTable[i2c_addressNACK]      = I2C_0_return_stop;
		I2C_0_status.callbackPayload[i2c_addressNACK]    = NULL;
		I2C_0_status.callbackTable[i2c_dataNACK]         = I2C_0_return_stop;
		I2C_0_status.callbackPayload[i2c_dataNACK]       = NULL;
		I2C_0_status.callbackTable[i2c_timeOut]          = I2C_0_return_reset;
		I2C_0_status.callbackPayload[i2c_timeOut]        = NULL;

TWI0.MCTRLB |= TWI_FLUSH_bm;
		TWI0.MSTATUS |= TWI_BUSSTATE_IDLE_gc;
		// Reset module
		TWI0.MSTATUS |= (TWI_RIF_bm | TWI_WIF_bm);

// uncomment the IRQ enable for an interrupt driven driver.
		TWI0.MCTRLA |= (TWI_RIEN_bm | TWI_WIEN_bm);

ret = I2C_NOERR;
	}
	return ret;
}

void I2C_0_set_address(i2c_address_t address)
{
	I2C_0_status.address = address;
}

/**
 * \brief Close the I2C interface
 *
 * \return Status of close operation.
 * \retval I2C_NOERR The I2C close was successful
 * \retval I2C_BUSY  The I2C close failed because the interface is busy
 * \retval I2C_FAIL  The I2C close failed with an error
 */
i2c_error_t I2C_0_close(void)
{
	i2c_error_t ret = I2C_BUSY;
	// Bus is in error state, reset I2C hardware and report error
	if (TWI0.MSTATUS & TWI_BUSERR_bm) {
		I2C_0_status.busy  = false;
		I2C_0_status.error = I2C_FAIL;
	}
	if (!I2C_0_status.busy) {
		I2C_0_status.inUse = 0;
		// close it down
		I2C_0_status.address = 0xff; // 8-bit address is invalid so this is FREE
		TWI0.MSTATUS |= (TWI_RIF_bm | TWI_WIF_bm);
		TWI0.MCTRLA &= ~(TWI_RIEN_bm | TWI_WIEN_bm);
		ret = I2C_0_status.error;
	}
	return ret;
}

/**
 * \brief Set timeout to be used for I2C operations. Uses the Timeout driver.
 *
 * \param[in] to Timeout in ticks
 *
 * \return Nothing
 */
void I2C_0_set_timeout(uint8_t to)
{
	TWI0.MCTRLA &= ~(TWI_RIEN_bm | TWI_WIEN_bm);
	I2C_0_status.timeout_value = to;
	TWI0.MCTRLA |= (TWI_RIEN_bm | TWI_WIEN_bm);
}

/**
 * \brief Set baud rate to be used for I2C operations.
 *
 * \param[in] baud to set the transfer speed
 *
 * \return Nothing
 */
void I2C_0_set_baud_rate(uint32_t baud)
{
	TWI0.MBAUD = (uint8_t)TWI0_BAUD(baud, 0); /* set MBAUD register */
}

/**
 * \brief Sets up the data buffer to use, and number of bytes to transfer
 *
 * \param[in] buffer Pointer to data buffer to use for read or write data
 * \param[in] bufferSize Number of bytes to read or write from slave
 *
 * \return Nothing
 */
void I2C_0_set_buffer(void *buffer, size_t bufferSize)
{
	if (I2C_0_status.bufferFree) {
// I2C_0_status.data_ptr    = buffer;
I2C_0_status.data_ptr    = (uint8_t*)buffer;        
		I2C_0_status.data_length = bufferSize;
		I2C_0_status.bufferFree  = false;
	}
}

/**
 * \brief Start an operation on an opened I2C interface
 *
 * \param[in] read Set to true for read, false for write
 *
 * \return Status of operation
 * \retval I2C_NOERR The I2C open was successful
 * \retval I2C_BUSY  The I2C open failed because the interface is busy
 * \retval I2C_FAIL  The I2C open failed with an error
 */
i2c_error_t I2C_0_master_operation(bool read)
{
	i2c_error_t ret = I2C_BUSY;
	if (!I2C_0_status.busy) {
		I2C_0_status.busy = true;
		ret               = I2C_NOERR;

if (read) {
			I2C_0_status.state = I2C_SEND_ADR_READ;
		} else {
			I2C_0_status.state = I2C_SEND_ADR_WRITE;
		}
		I2C_0_master_isr();
	}
	return ret;
}

/**
 * \brief Identical to I2C_0_master_operation(true);
 */
i2c_error_t I2C_0_master_read(void)
{
	return I2C_0_master_operation(true);
}

/**
 * \brief Identical to I2C_0_master_operation(false);
 */
i2c_error_t I2C_0_master_write(void)
{
	return I2C_0_master_operation(false);
}

/************************************************************************/
/* Helper Functions                                                     */
/************************************************************************/

static i2c_fsm_states_t I2C_0_do_I2C_RESET(void)
{
	TWI0.MCTRLB |= TWI_FLUSH_bm;
	TWI0.MSTATUS |= TWI_BUSSTATE_IDLE_gc;
	I2C_0_status.busy  = false; // Bus Free
	I2C_0_status.error = I2C_NOERR;
	return I2C_RESET; // park the FSM on reset
}

static i2c_fsm_states_t I2C_0_do_I2C_IDLE(void)
{
	I2C_0_status.busy  = false; // Bus Free
	I2C_0_status.error = I2C_NOERR;
	return I2C_IDLE; // park the FSM on IDLE
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_RESTART_READ(void)
{
	return I2C_0_do_I2C_SEND_ADR_READ();
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_RESTART_WRITE(void)
{
	return I2C_0_do_I2C_SEND_ADR_WRITE();
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_RESTART(void)
{
	return I2C_0_do_I2C_SEND_ADR_READ();
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_STOP(void)
{
	TWI0.MCTRLB |= TWI_MCMD_STOP_gc;
	return I2C_0_do_I2C_IDLE();
}

// TODO: probably need 2 addressNACK's one from read and one from write.
//       the do NACK before RESTART or STOP is a special case that a new state simplifies.
static i2c_fsm_states_t I2C_0_do_I2C_DO_ADDRESS_NACK(void)
{
	I2C_0_status.addressNACKCheck = 0;
	I2C_0_status.error            = I2C_FAIL;
	switch (I2C_0_status.callbackTable[i2c_addressNACK](I2C_0_status.callbackPayload[i2c_addressNACK])) {
	case i2c_restart_read:
		return I2C_0_do_I2C_SEND_RESTART_READ();
	case i2c_restart_write:
		return I2C_0_do_I2C_SEND_RESTART_WRITE();
	default:
		return I2C_0_do_I2C_SEND_STOP();
	}
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_ADR_READ(void)
{

I2C_0_status.addressNACKCheck = 1;
	TWI0.MADDR                    = I2C_0_status.address << 1 | 1;
	return I2C_RX;
}

static i2c_fsm_states_t I2C_0_do_I2C_SEND_ADR_WRITE(void)
{

I2C_0_status.addressNACKCheck = 1;
	TWI0.MADDR                    = I2C_0_status.address << 1;
	return I2C_TX;
}

static i2c_fsm_states_t I2C_0_do_I2C_RX_DO_ACK(void)
{
	TWI0.MCTRLB &= ~(1 << TWI_ACKACT_bp);
	return I2C_RX;
}

static i2c_fsm_states_t I2C_0_do_I2C_TX_DO_ACK(void)
{
	TWI0.MCTRLB &= ~(1 << TWI_ACKACT_bp);
	return I2C_TX;
}

static i2c_fsm_states_t I2C_0_do_I2C_DO_NACK_STOP(void)
{
	TWI0.MCTRLB |= TWI_ACKACT_NACK_gc;
	TWI0.MCTRLB |= TWI_MCMD_STOP_gc;
	return I2C_0_do_I2C_IDLE();
}

static i2c_fsm_states_t I2C_0_do_I2C_DO_NACK_RESTART(void)
{
	TWI0.MCTRLB |= TWI_ACKACT_NACK_gc;
	return I2C_SEND_RESTART;
}

static i2c_fsm_states_t I2C_0_do_I2C_TX(void)
{
	if ((TWI0.MSTATUS & TWI_RXACK_bm)) // Slave replied with NACK
	{
		switch (I2C_0_status.callbackTable[i2c_dataNACK](I2C_0_status.callbackPayload[i2c_dataNACK])) {
		case i2c_restart_read:
			return I2C_0_do_I2C_SEND_RESTART_READ();
		case i2c_restart_write:
			return I2C_0_do_I2C_SEND_RESTART_WRITE();
		default:
		case i2c_continue:
		case i2c_stop:
			return I2C_0_do_I2C_SEND_STOP();
		}
	} else {
		I2C_0_status.addressNACKCheck = 0;
		TWI0.MDATA                    = *I2C_0_status.data_ptr++;
		return (--I2C_0_status.data_length) ? I2C_TX : I2C_TX_EMPTY;
	}
}

static i2c_fsm_states_t I2C_0_do_I2C_RX(void)
{
	I2C_0_status.addressNACKCheck = 0;

if (I2C_0_status.data_length == 1)
		TWI0.MCTRLB |= TWI_ACKACT_NACK_gc; // Next byte will be last to be received, setup NACK
	else
		TWI0.MCTRLB &= ~(1 << TWI_ACKACT_bp); // More bytes to receive, setup ACK

if (--I2C_0_status.data_length) {
		*I2C_0_status.data_ptr = TWI0.MDATA;
		I2C_0_status.data_ptr++;
		TWI0.MCTRLB |= TWI_MCMD_RECVTRANS_gc;
		return I2C_RX;
	} else {
		*I2C_0_status.data_ptr = TWI0.MDATA;
		I2C_0_status.data_ptr++;
		I2C_0_status.bufferFree = true;
		switch (I2C_0_status.callbackTable[i2c_dataComplete](I2C_0_status.callbackPayload[i2c_dataComplete])) {
		case i2c_restart_write:
		case i2c_restart_read:
			return I2C_0_do_I2C_DO_NACK_RESTART();
		default:
		case i2c_continue:
		case i2c_stop:
			return I2C_0_do_I2C_DO_NACK_STOP();
		}
	}
}

static i2c_fsm_states_t I2C_0_do_I2C_TX_EMPTY(void)
{
	if ((TWI0.MSTATUS & TWI_RXACK_bm)) // Slave replied with NACK
	{
		switch (I2C_0_status.callbackTable[i2c_dataNACK](I2C_0_status.callbackPayload[i2c_dataNACK])) {
		case i2c_restart_read:
			return I2C_0_do_I2C_SEND_RESTART_READ();
		case i2c_restart_write:
			return I2C_0_do_I2C_SEND_RESTART_WRITE();
		default:
		case i2c_continue:
		case i2c_stop:
			return I2C_0_do_I2C_SEND_STOP();
		}
	} else {
		I2C_0_status.bufferFree = true;
		switch (I2C_0_status.callbackTable[i2c_dataComplete](I2C_0_status.callbackPayload[i2c_dataComplete])) {
		case i2c_restart_read:
			return I2C_0_do_I2C_SEND_RESTART_READ();
		case i2c_restart_write:
			return I2C_0_do_I2C_SEND_RESTART_WRITE();
		case i2c_continue:
			return I2C_0_do_I2C_TX();
		default:
		case i2c_stop:
			return I2C_0_do_I2C_SEND_STOP();
		}
	}
}

static i2c_fsm_states_t I2C_0_do_I2C_BUS_COLLISION(void)
{
	// Clear bus collision status flag
	TWI0.MSTATUS |= TWI_ARBLOST_bm;
	;
	I2C_0_status.error = I2C_FAIL;
	switch (I2C_0_status.callbackTable[i2c_writeCollision](I2C_0_status.callbackPayload[i2c_writeCollision])) {
	case i2c_restart_read:
		return I2C_0_do_I2C_SEND_RESTART_READ();
	case i2c_restart_write:
		return I2C_0_do_I2C_SEND_RESTART_WRITE();
	default:
		return I2C_0_do_I2C_RESET();
	}
}

static i2c_fsm_states_t I2C_0_do_I2C_BUS_ERROR(void)
{
	TWI0.MCTRLB |= TWI_FLUSH_bm;
	TWI0.MSTATUS |= TWI_BUSSTATE_IDLE_gc;
	I2C_0_status.busy  = false;
	I2C_0_status.error = I2C_FAIL;
	return I2C_RESET; // park the FSM on reset
}

stateHandlerFunction *I2C_0_fsmStateTable[] = {
    I2C_0_do_I2C_IDLE,               // I2C_IDLE
    I2C_0_do_I2C_SEND_ADR_READ,      // I2C_SEND_ADR_READ
    I2C_0_do_I2C_SEND_ADR_WRITE,     // I2C_SEND_ADR_WRITE
    I2C_0_do_I2C_TX,                 // I2C_TX
    I2C_0_do_I2C_RX,                 // I2C_RX
    I2C_0_do_I2C_TX_EMPTY,           // I2C_TX_EMPTY
    I2C_0_do_I2C_SEND_RESTART_READ,  // I2C_SEND_RESTART_READ
    I2C_0_do_I2C_SEND_RESTART_WRITE, // I2C_SEND_RESTART_WRITE
    I2C_0_do_I2C_SEND_RESTART,       // I2C_SEND_RESTART
    I2C_0_do_I2C_SEND_STOP,          // I2C_SEND_STOP
    I2C_0_do_I2C_RX_DO_ACK,          // I2C_RX_DO_ACK
    I2C_0_do_I2C_TX_DO_ACK,          // I2C_TX_DO_ACK
    I2C_0_do_I2C_DO_NACK_STOP,       // I2C_RX_DO_NACK_STOP
    I2C_0_do_I2C_DO_NACK_RESTART,    // I2C_RX_DO_NACK_RESTART
    I2C_0_do_I2C_RESET,              // I2C_RESET
    I2C_0_do_I2C_DO_ADDRESS_NACK,    // I2C_ADDRESS_NACK
    I2C_0_do_I2C_BUS_COLLISION,      // I2C_BUS_COLLISION
    I2C_0_do_I2C_BUS_ERROR           // I2C_BUS_ERROR
};

#include <avr/interrupt.h>
ISR(TWI0_TWIM_vect)
{
	I2C_0_master_isr();
}

void I2C_0_master_isr(void)
{
	TWI0.MSTATUS |= (TWI_RIF_bm | TWI_WIF_bm);

// NOTE: We are ignoring the Write Collision flag.

// Address phase received NACK from slave, override next state
	if (I2C_0_status.addressNACKCheck && (TWI0.MSTATUS & TWI_RXACK_bm)) {
		I2C_0_status.state = I2C_ADDRESS_NACK; // State Override
	}

// Bus arbitration lost to another master, override next state
	if (TWI0.MSTATUS & TWI_ARBLOST_bm) {
		I2C_0_status.state = I2C_BUS_COLLISION; // State Override
	}

// Bus error, override next state
	if (TWI0.MSTATUS & TWI_BUSERR_bm) {
		I2C_0_status.state = I2C_BUS_ERROR; // State Override
	}

I2C_0_status.state = I2C_0_fsmStateTable[I2C_0_status.state]();
}

static i2c_operations_t I2C_0_return_reset(void *p)
{
	return i2c_reset_link;
}

static void I2C_0_set_callback(i2c_callback_index idx, i2c_callback cb, void *p)
{
	if (cb) {
		I2C_0_status.callbackTable[idx]   = cb;
		I2C_0_status.callbackPayload[idx] = p;
	} else {
		I2C_0_status.callbackTable[idx]   = I2C_0_return_stop;
		I2C_0_status.callbackPayload[idx] = NULL;
	}
}

/**
 * \file
 *
 * \brief I2C Master driver example.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

#ifndef I2C_MASTER_EXAMPLE_H
#define I2C_MASTER_EXAMPLE_H

uint8_t I2C_0_test_i2c_master(void);

#endif /* I2C_MASTER_EXAMPLE_H */

/**
 * \file
 *
 * \brief I2C Master driver example.
 *
 (c) 2020 Microchip Technology Inc. and its subsidiaries.
 *
 */

// #include <atmel_start.h>
// #include <i2c_types.h>
// #include <i2c_simple_master.h>
// #include <utils/atomic.h>

#define slave_adr 0x4f
#define slave_reg_adr 0x0

uint8_t read_data[2];

/** Structure passed into read_handler to describe the actions to be performed by the handler */
typedef struct {
	uint8_t *data;
	uint8_t  size;
} transfer_descriptor_t;

/** This callback is called when the initial write of the pointer register has finished.
    This callback controls the second phase of the I2C transaction, the read of the
    targeted register after a REPEATED START.
*/
i2c_operations_t I2C_0_read_handler(void *d)
{
	transfer_descriptor_t *desc = (transfer_descriptor_t *)d;
	I2C_0_set_buffer((void *)desc->data, desc->size);
	// Set callback to terminate transfer and send STOP after read is complete
	I2C_0_set_data_complete_callback(i2c_cb_return_stop, NULL);
	return i2c_restart_read; // Send REPEATED START before read
}

/** Performs the following transfer sequence:
1. Send SLA+W, Data1
2. Send RepeatedStart, SLA+R, Read Data1, Read Data2
3. Send Stop

This transfer sequence is typically done to first write to the slave the address in
the slave to read from, thereafter to read N bytes from this address.
*/
i2c_error_t I2C_0_do_transfer(uint8_t adr, uint8_t *data, uint8_t size)
{
	/* timeout is used to get out of twim_release, when there is no device connected to the bus*/
	uint16_t              timeout = I2C_TIMEOUT;
	transfer_descriptor_t d       = {data, size};

while (I2C_BUSY == I2C_0_open(slave_adr) && --timeout)
		; // sit here until we get the bus..
	if (!timeout)
		return I2C_BUSY;

// This callback specifies what to do after the first write operation has completed
	// The parameters to the callback are bundled together in the aggregate data type d.
	I2C_0_set_data_complete_callback(I2C_0_read_handler, &d);
	// If we get an address NACK, then try again by sending SLA+W
	I2C_0_set_address_nack_callback(i2c_cb_restart_write, NULL);
	// Transmit specified number of bytes
	I2C_0_set_buffer((void *)&adr, 1);
	// Start a Write operation
	I2C_0_master_operation(false);
	timeout = I2C_TIMEOUT;
	while (I2C_BUSY == I2C_0_close() && --timeout)
		; // sit here until finished.
	if (!timeout)
		return I2C_FAIL;

return I2C_NOERR;
}

uint8_t I2C_0_test_i2c_master(void)
{

I2C_0_do_transfer(slave_reg_adr, read_data, 2);
	// If we get here, everything was OK
	return 1;
}

int main(){

//port code not brought in, which would also enable twi pin pullups
    I2C_0_init();

sei(); //not sure where they do this
    while(1){
        I2C_0_test_i2c_master();
        }

}