Compiler Explorer

Source code

; ModuleID = 'add_sub_sat-inseltpoison.ll'
source_filename = "add_sub_sat-inseltpoison.ll"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"

define <4 x i16> @notVectorized(<4 x i16> %arg0, <4 x i16> %arg1) #0 {
bb:
  %arg0.2 = extractelement <4 x i16> %arg0, i64 2
  %arg0.3 = extractelement <4 x i16> %arg0, i64 3
  %arg1.2 = extractelement <4 x i16> %arg1, i64 2
  %arg1.3 = extractelement <4 x i16> %arg1, i64 3
  %0 = shufflevector <4 x i16> %arg0, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
  %1 = shufflevector <4 x i16> %arg1, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
  %2 = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %0, <2 x i16> %1)
  %add.2 = call i16 @llvm.uadd.sat.i16(i16 %arg0.2, i16 %arg1.2)
  %add.3 = call i16 @llvm.uadd.sat.i16(i16 %arg0.3, i16 %arg1.3)
  %3 = shufflevector <2 x i16> %2, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
  %ins.2 = insertelement <4 x i16> %3, i16 %add.2, i64 2
  %ins.3 = insertelement <4 x i16> %ins.2, i16 %add.3, i64 3
  ret <4 x i16> %ins.3
}

define <4 x i16> @vectorized(<4 x i16> %arg0, <4 x i16> %arg1) #0 {
bb:
  %0 = shufflevector <4 x i16> %arg0, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
  %1 = shufflevector <4 x i16> %arg1, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
  %2 = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %0, <2 x i16> %1)
  %3 = shufflevector <4 x i16> %arg0, <4 x i16> poison, <2 x i32> <i32 2, i32 3>
  %4 = shufflevector <4 x i16> %arg1, <4 x i16> poison, <2 x i32> <i32 2, i32 3>
  %5 = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %3, <2 x i16> %4)
  %ins.31 = shufflevector <2 x i16> %2, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x i16> %ins.31
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.uadd.sat.i16(i16, i16) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.usub.sat.i16(i16, i16) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.sadd.sat.i16(i16, i16) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.ssub.sat.i16(i16, i16) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.uadd.sat.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.usub.sat.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.sadd.sat.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.ssub.sat.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #2

attributes #0 = { "target-cpu"="gfx900" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx900" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }