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llvm source #1
Output
Compile to binary object
Link to binary
Execute the code
Intel asm syntax
Demangle identifiers
Verbose demangling
Filters
Unused labels
Library functions
Directives
Comments
Horizontal whitespace
Debug intrinsics
Compiler
clang (assertions trunk)
clang (trunk)
clang 10.0.0
clang 10.0.1
clang 11.0.0
clang 11.0.1
clang 12.0.0
clang 12.0.1
clang 13.0.0
clang 14.0.0
clang 15.0.0
clang 16.0.0
clang 17.0.1
clang 18.1.0
clang 19.1.0
clang 4.0.1
clang 5.0.0
clang 6.0.0
clang 7.0.0
clang 8.0.0
clang 9.0.0
llc (assertions trunk)
llc (trunk)
llc 10.0.0
llc 10.0.1
llc 11.0.0
llc 11.0.1
llc 12.0.0
llc 12.0.1
llc 13.0.0
llc 14.0.0
llc 15.0.0
llc 16.0.0
llc 17.0.1
llc 18.1.0
llc 19.1.0
llc 3.2
llc 3.3
llc 3.9.1
llc 4.0.0
llc 4.0.1
llc 5.0.0
llc 6.0.0
llc 7.0.0
llc 8.0.0
llc 9.0.0
opt (assertions trunk)
opt (trunk)
opt 10.0.0
opt 10.0.1
opt 11.0.0
opt 11.0.1
opt 12.0.0
opt 12.0.1
opt 13.0.0
opt 14.0.0
opt 15.0.0
opt 16.0.0
opt 17.0.1
opt 18.1.0
opt 19.1.0
opt 3.2
opt 3.3
opt 3.9.1
opt 4.0.0
opt 4.0.1
opt 5.0.0
opt 6.0.0
opt 7.0.0
opt 8.0.0
opt 9.0.0
Options
Source code
define void @vf16(<48 x i16>* %in.vec, <16 x i16>* %out.vec0, <16 x i16>* %out.vec1, <16 x i16>* %out.vec2) nounwind { %wide.vec = load <48 x i16>, <48 x i16>* %in.vec, align 32 tail call void asm sideeffect "# LLVM-MCA-BEGIN", "~{dirflag},~{fpsr},~{flags}"() %strided.vec0 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %strided.vec1 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %strided.vec2 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> tail call void asm sideeffect "# LLVM-MCA-END", "~{dirflag},~{fpsr},~{flags}"() store <16 x i16> %strided.vec0, <16 x i16>* %out.vec0, align 32 store <16 x i16> %strided.vec1, <16 x i16>* %out.vec1, align 32 store <16 x i16> %strided.vec2, <16 x i16>* %out.vec2, align 32 ret void }
analysis source #2
Output
Compile to binary object
Link to binary
Execute the code
Intel asm syntax
Demangle identifiers
Verbose demangling
Filters
Unused labels
Library functions
Directives
Comments
Horizontal whitespace
Debug intrinsics
Compiler
OSACA (0.6.1)
llvm-mca (assertions trunk)
llvm-mca (trunk)
Options
Source code
vmovdqa ymm4, ymmword ptr [rip + .LCPI0_0] # ymm4 = <255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255> vpblendvb ymm4, ymm3, ymm2, ymm4 vpermq ymm5, ymm4, 78 # ymm5 = ymm4[2,3,0,1] vpblendw ymm4, ymm4, ymm5, 146 # ymm4 = ymm4[0],ymm5[1],ymm4[2,3],ymm5[4],ymm4[5,6],ymm5[7],ymm4[8],ymm5[9],ymm4[10,11],ymm5[12],ymm4[13,14],ymm5[15] vpshufb ymm4, ymm4, ymmword ptr [rip + .LCPI0_1] # ymm4 = ymm4[0,1,6,7,12,13,2,3,4,5,14,15,8,9,10,11,16,17,22,23,28,29,18,19,20,21,30,31,24,25,26,27] vpblendw xmm5, xmm0, xmm1, 36 # xmm5 = xmm0[0,1],xmm1[2],xmm0[3,4],xmm1[5],xmm0[6,7] vpshufb xmm5, xmm5, xmmword ptr [rip + .LCPI0_2] # xmm5 = xmm5[u,u,u,u,u,u,2,3,8,9,14,15,4,5,10,11] vinserti128 ymm5, ymm0, xmm5, 1 vpblendw ymm5, ymm5, ymm4, 7 # ymm5 = ymm4[0,1,2],ymm5[3,4,5,6,7],ymm4[8,9,10],ymm5[11,12,13,14,15] vpshufhw xmm4, xmm4, 198 # xmm4 = xmm4[0,1,2,3,6,5,4,7] vpblendd ymm4, ymm4, ymm5, 240 # ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] vmovdqa ymm5, ymmword ptr [rip + .LCPI0_3] # ymm5 = <255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255> vpblendvb ymm5, ymm2, ymm3, ymm5 vpermq ymm6, ymm5, 78 # ymm6 = ymm5[2,3,0,1] vpblendw ymm5, ymm5, ymm6, 36 # ymm5 = ymm5[0,1],ymm6[2],ymm5[3,4],ymm6[5],ymm5[6,7,8,9],ymm6[10],ymm5[11,12],ymm6[13],ymm5[14,15] vpshufb ymm5, ymm5, ymmword ptr [rip + .LCPI0_4] # ymm5 = ymm5[2,3,8,9,14,15,4,5,12,13,10,11,0,1,6,7,18,19,24,25,30,31,20,21,28,29,26,27,16,17,22,23] vpblendw xmm6, xmm1, xmm0, 36 # xmm6 = xmm1[0,1],xmm0[2],xmm1[3,4],xmm0[5],xmm1[6,7] vpshufb xmm6, xmm6, xmmword ptr [rip + .LCPI0_5] # xmm6 = xmm6[u,u,u,u,u,u,4,5,10,11,0,1,6,7,12,13] vinserti128 ymm6, ymm0, xmm6, 1 vpblendw ymm6, ymm6, ymm5, 7 # ymm6 = ymm5[0,1,2],ymm6[3,4,5,6,7],ymm5[8,9,10],ymm6[11,12,13,14,15] vpshufhw xmm5, xmm5, 57 # xmm5 = xmm5[0,1,2,3,5,6,7,4] vpblendd ymm5, ymm5, ymm6, 240 # ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] vmovdqa ymm6, ymmword ptr [rip + .LCPI0_6] # ymm6 = <u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u> vpblendvb ymm2, ymm2, ymm3, ymm6 vextracti128 xmm3, ymm2, 1 vpblendw ymm2, ymm2, ymm3, 73 # ymm2 = ymm3[0],ymm2[1,2],ymm3[3],ymm2[4,5],ymm3[6],ymm2[7],ymm3[8],ymm2[9,10],ymm3[11],ymm2[12,13],ymm3[14],ymm2[15] vpshufb ymm2, ymm2, ymmword ptr [rip + .LCPI0_7] # ymm2 = ymm2[4,5,10,11,0,1,6,7,12,13,2,3,8,9,14,15,20,21,26,27,u,u,u,u,u,u,u,u,u,u,u,u] vpblendw xmm0, xmm0, xmm1, 146 # xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4],xmm0[5,6],xmm1[7] vpshufb xmm0, xmm0, xmmword ptr [rip + .LCPI0_8] # xmm0 = xmm0[u,u,u,u,0,1,6,7,12,13,2,3,8,9,14,15] vinserti128 ymm0, ymm0, xmm0, 1 vpblendd ymm0, ymm2, ymm0, 224 # ymm0 = ymm2[0,1,2,3,4],ymm0[5,6,7]
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